Guard ring structure and method for forming the same

1. A guard ring structure, comprising

a semiconductor substrate with a circuit region encircled by a first ring and a second ring, wherein the semiconductor substrate has a first dopant type, and each of the first and second rings comprises:

a first doping region embedded in a portion of the semiconductor substrate, having a second dopant type opposite to the first dopant type; and

an interconnect element formed over the semiconductor substrate, covering the first doping region;

wherein the first doping region of the first ring is separated from the first doping region of the second ring by a well region.

2. The guard ring structure as claimed in claim 1 , further comprising:

a plurality of separated second doping regions formed in a top portion of the semiconductor substrate, overlying the first doping region and having the first dopant type, wherein the interconnect element covers the second doping regions; and

an isolation region formed over the semiconductor substrate and between and adjacent to the second doping regions.

3. The guard ring structure as claimed in claim 1 , wherein the interconnect element comprises a plurality of levels of conductive via and conductive line that are alternately stacked over the semiconductor substrate.

4. The guard ring structure as claimed in claim 3 , wherein the conductive via and conductive line comprise aluminum or copper.

5. The guard ring structure as claimed in claim 2 , wherein the second doping regions comprise a resistivity lower than that of the semiconductor substrate.

6. The guard ring structure as claimed in claim 1 , wherein the first dopant type is p-type, and the second dopant type is n-type.

7. The guard ring structure as claimed in claim 1 , wherein the well region is embedded in the semiconductor substrate and disposed adjacent to the first doping region, and the well region has the first conductivity type.

8. The guard ring structure as claimed in claim 7 , wherein the well region comprises a resistivity lower than that of the semiconductor substrate.

9. The guard ring structure as claimed in claim 2 , wherein the isolation region is a shallow trench isolation (STI) region.

10. The guard ring structure as claimed in claim 2 , wherein the interconnect element comprises a plurality of dielectric layers sequentially stacked over the semiconductor substrate.

11. The guard ring structure as claimed in claim 10 , wherein a plurality of conductive vias and conductive lines alternately formed in one of the plurality of dielectric layers.

12. The guard ring structure as claimed in claim 2 , further comprising:

a metallic-silicide region, provided at an interface between the first doping region and the interconnect element.

13. The guard ring structure as claimed in claim 1 , wherein the first doping region is separated from the interconnect element by a second doping region.

14. The guard ring structure as claimed in claim 13 , wherein the second doping region has the first dopant type.

15. The guard ring structure as claimed in claim 13 , wherein the first doping region is wider than the second doping region.

16. The guard ring structure as claimed in claim 13 , wherein the well region is embedded in the semiconductor substrate and disposed adjacent to the first doping region, and the well region has the first conductivity type.

17. The guard ring structure as claimed in claim 16 , wherein the first doping region and the well region substantially have the same depth.

18. The guard ring structure as claimed in claim 16 , wherein the second doping region connects the first doping region without connecting the well region.

19. The guard ring structure as claimed in claim 16 , wherein the first doping region is separated from the interconnect element further by an isolation region adjacent to the second doping region.

20. The guard ring structure as claimed in claim 19 , wherein the isolation region contacts the first doping region and the well region.