System and method using cascaded single partity check coding
View Patent ↗A system and method including a parity bit encoder for encoding each n−3 bits of data to be transmitted with three parity check bits to produce blocks of n bits (n−3 information bits plus three parity bits associated with the n information bits). Each of the blocks of n bits are Gray mapped to three QAM symbols that are modulated onto an optical wavelength and transmitted to a receiver. A maximum a posteriori (MAP) decoder is used at the receiver to correct for cycle slip.
1. A system comprising:
a parity bit encoder configured to encode successive blocks of n−3 bits with three parity bits to provide successive blocks of n bits;
a Gray mapper coupled to said parity bit encoder and configured to map each one of said blocks of n bits to three associated quadrature amplitude modulated (QAM) symbols;
a modulator coupled to said Gray mapper and configured to modulate an optical signal in response to an output of said Gray mapper to provide a modulated optical signal comprising said three associated QAM symbols;
a detector for receiving said modulated optical signal and providing an electrical signal representative of said optical signal; and
a de-mapper configured to provide a de-mapper output representative of said blocks of n−3 bits in response to said electrical signal.
2. A system according to claim 1 , wherein said three parity bits are calculated according to the following equations:
P
1
=
XOR
(
x
1
,
x
2
,
…
,
x
2
n
3
-
1
)
_
;
P
2
=
XOR
(
x
i
+
j
)
,
∀
i
,
j
where
j
∈
(
0
,
n
3
,
2
n
3
)
,
i
∈
{
{
1
,
…
n
6
}
for
j
∈
{
0
,
n
3
}
{
1
,
…
n
6
-
1
}
for
j
=
2
n
3
;
and
P
3
=
XOR
(
x
1
,
x
2
,
…
,
x
n
-
3
,
P
1
,
P
2
)
_
,
where P 1 , P 2 , and P 3 , are first, second and third ones of said three parity bits, respectively, and x 1 , x 2 , . . . x n−3 , are the n−3 bits, respectively.
3. A system according to claim 2 , wherein said parity bit encoder is configured to position said three parity bits within said n bits according to the following:
P 1 is positioned anywhere in the first 2n/3 bits;
P 2 is positioned anywhere between the 2n/3+1 th bit and the 5n/6 th bit; and
P 3 is positioned anywhere between the 2n/3+1 th and the n th bits that is different from the position of P 2 .
4. A system according to claim 1 , wherein said de-mapper is configured to provide said de-mapper output by selecting a second one of said three associated QAM symbols based on a Hamming weight of a first one of said three associated QAM symbols.
5. A system according to claim 4 , wherein said de-mapper is configured to provide said de-mapper output by selecting a third one of said three associated QAM symbols based a Hamming weight of the
log
2
(
M
2
)
2
most significant bits of said first and second ones of said three associated QAM symbols, where M is a number of bits represented by each symbol of said three associated QAM symbols.
6. A system according to claim 1 , said de-mapper being further configured to cause correction of cycle slip using parity indicated by said three parity bits.
7. A system according to claim 1 , said system further comprising
a demultiplexer configured to receive a serial input data stream and demultiplex said serial input data stream into a plurality of demultipexed data streams;
a plurality of forward error correction (FEC) encoders, each of said FEC encoders being configured to encode an associated one of said demultiplexed data streams using a FEC code and provide an associated FEC encoded output; and
an interleaver coupled said plurality of FEC encoders and configured to provide an interleaved output comprising said successive blocks of n−3 bits to said parity bit encoder.
8. A system according to claim 1 , said system further comprising
a de-interleaver coupled to said de-mapper and configured to provide a plurality of de-interleaved outputs in response to said de-mapper output; and
a plurality of FEC decoders, each of said FEC decoders being configured to receive an associated one of said de-interleaved outputs and provide an associated FEC decoded output signal.
9. An optical signal receiver comprising:
a detector for receiving a modulated optical signal representing blocks of n bits comprising n−3 information bits and three parity bits mapped to three associated quadrature amplitude modulated (QAM) signals and for providing an electrical signal representative of said optical signal; and
a de-mapper configured to provide a de-mapper output representative of said n−3 information bits in response to said electrical signal.
10. An optical signal receiver according to claim 9 , wherein said de-mapper is configured to provide said de-mapper output by selecting a second one of said three associated QAM symbols based on a Hamming weight of a first one of said three associated QAM symbols.
11. An optical signal receiver according to claim 10 , wherein said de-mapper is configured to provide said de-mapper output by selecting a third one of said three associated QAM symbols based a Hamming weight of the
log
2
(
M
2
)
2
most significant bits of said first and second ones of said three associated QAM symbols, where M is a number of bits represented by each symbol of said three associated QAM symbols.
12. An optical signal receiver according to claim 9 , said de-mapper being further configured to cause correction of cycle slip using parity indicated by said three parity bits.
13. An optical signal receiver according to claim 9 , said system further comprising
a de-interleaver coupled to said de-mapper and configured to provide a plurality of de-interleaved outputs in response to said de-mapper output; and
a plurality of FEC decoders, each of said FEC decoders being configured to receive an associated one of said de-interleaved outputs and provide an associated FEC decoded output signal.
14. A method comprising:
encoding successive blocks of n−3 bits of a signal with three parity bits to provide successive blocks of n bits;
Gray mapping said successive blocks of n bits to three associated quadrature amplitude modulated (QAM) symbols;
modulating said three associated QAM symbols on an optical carrier wavelength to provide a modulated optical signal;
detecting said modulated optical signal to provide an electrical signal; and
de-mapping said three associated QAM symbols from said electrical signal to provide a de-mapper output representative of said blocks of n−3 bits.
15. A method according to claim 14 , wherein said encoding comprises calculating said three parity according to the following equations:
P
1
=
XOR
(
x
1
,
x
2
,
…
,
x
2
n
3
-
1
)
_
;
P
2
=
XOR
(
x
i
+
j
)
,
∀
i
,
j
where
j
∈
(
0
,
n
3
,
2
n
3
)
,
i
∈
{
{
1
,
…
n
6
}
for
j
∈
{
0
,
n
3
}
{
1
,
…
n
6
-
1
}
for
j
=
2
n
3
;
and
P
3
=
XOR
(
x
1
,
x
2
,
…
,
x
n
-
3
,
P
1
,
P
2
)
_
,
where P 1 , P 2 , and P 3 , are first, second and third ones of said three parity bits, respectively, and x 1 , x 2 , . . . x n− 3, are the n−3 bits, respectively.
16. A method according to claim 15 , wherein said encoding comprises positioning said three parity bits within said n bits according to the following:
P 1 is positioned anywhere in the first 2n/3 bits.
P 2 is positioned anywhere between the 2n/3+1 th bit and the 5n/6 th bit; and
P 3 is positioned anywhere between the 2n/3+1 th and the n th bits that is different from the position of P 2 .
17. A method according to claim 14 , wherein said de-mapping comprises selecting a second one of said three associated QAM symbols based on a Hamming weight of a first one of said three associated QAM symbols.
18. A method according to claim 17 , wherein said de-mapping comprises selecting a third one of said three associated QAM symbols based a Hamming weight of the
log
2
(
M
2
)
2
most significant bits of said first and second ones of said three associated QAM symbols, where M is a number of bits represented by each symbol of said three associated QAM symbols.
19. A method according to claim 14 , wherein said de-mapping comprises correcting cycle slip using parity indicated by said three parity bits.
20. A method according to claim 14 , said method further comprising
demultiplexing an input signal to provide a plurality of demultiplexed data streams;
encoding each of said plurality of demultiplexed data streams using an forward error correction (FEC) code to provide a plurality of FEC encoded outputs; and
interleaving said FEC encoded outputs to provide said successive blocks of n−3 bits.