Computing system utilizing dispersed storage

1. A memory controller comprises:

an input unit operable to receive a read request regarding a data segment; and

a processing unit operable to:

interpret the read request to determine whether the data segment is encoded using an error encoding dispersal function and stored as a set of encoded data slices;

when the data segment is stored as the set of encoded data slices:

identify one or more memories that are storing at least a threshold number of encoded data slices of the set of encoded data slices, wherein memories of the one or more memories includes at least one of:

a main memory of a computing device; and

one or more of a plurality of memory components of the computing device; and

address the one or more memories to retrieve the at least the threshold number of encoded data slices;

when the data segment is not encoded:

identify one of the one or more memories; and

address the one of the one or more memories to retrieve the data segment.

2. The memory controller of claim 1 , wherein the processing unit is further operable to interpret the read request by:

interpreting information of the read request, wherein the information includes one or more of: an object identifier (ID) of the data segment, a filename of the data segment, a virtual memory address, a requester ID, a process ID, a vault ID, a vault lookup, a predetermination, a list, a command, a message.

3. The memory controller of claim 1 , wherein the input unit is operable to:

receive the read request from a requester, wherein the requester is one of: a processing module, a video processing unit, an input/output controller, an input/output interface, a peripheral component controller, and a direct memory access unit.

4. The memory controller of claim 1 further comprises:

an output unit operable to:

output a set of retrieval requests to the one or more memories to retrieve the at least the threshold number of encoded data slices in accordance with the addressing the one or more memories; and

output a retrieval request to the one of one or more memories to retrieve the data segment in accordance with the addressing the one of the one or more memories; and

the input module is further operable to:

receive the at least the threshold number of encoded data slices from the one or more memories; and

receive the data segment from the one of the one or more memories.

5. The memory controller of claim 1 further comprises:

a dispersed storage processing module operable to decode the set of encoded data slices using the error encoding dispersal function to recapture the data segment; and

an output unit to send the recaptured data segment to a requestor issuing the read request.

6. The memory controller of claim 1 , wherein the plurality of memory components comprises at least one of:

one or more non-core local hard disk drives;

one or more non-core local solid state memory devices;

one or more local area network (LAN) memory devices; and

one or more wide area network (WAN) memory devices.

7. A memory controller comprises:

an input unit operable to receive a write request regarding a data segment; and

a processing unit operable to:

interpret the write request to determine whether the data segment is to be encoded using an error encoding dispersal function and to be stored as a set of encoded data slices;

when the data segment is to be stored as the set of encoded data slices:

identify one or more memories to store the set of encoded data slices, wherein memories of the one or more memories includes at least one of:

a main memory of a computing device; and

one or more of a plurality of memory components of the computing device; and

address the one or more memories to store the set of encoded data slices;

when the data segment is not to be encoded:

identify one of the one or more memories; and

address the one of the one or more memories to store the data segment.

8. The memory controller of claim 7 , wherein the processing unit is further operable to interpret the write request by:

interpreting information of the write request, wherein the information includes one or more of: an object identifier (ID) of the data segment, a filename of the data segment, a virtual memory address, a requester ID, a process ID, a vault ID, a vault lookup, a predetermination, a list, a command, a message.

9. The memory controller of claim 7 , wherein the input unit is operable to:

receive the write request from a requester, wherein the requester is one of: a processing module, a video processing unit, an input/output controller, an input/output interface, a peripheral component controller, and a direct memory access unit.

10. The memory controller of claim 7 further comprises:

an output unit operable to:

output a set of write requests to the one or more memories to write the set of encoded data slices in accordance with the addressing the one or more memories; and

output a write request to the one of one or more memories to write the data segment in accordance with the addressing the one of the one or more memories.

11. The memory controller of claim 7 further comprises:

a dispersed storage processing module operable to encode the data segment using the error encoding dispersal function to produce the set of encoded data slices.

12. The memory controller of claim 7 , wherein the plurality of memory components comprises at least one of:

one or more non-core local hard disk drives;

one or more non-core local solid state memory devices;

one or more local area network (LAN) memory devices; and

one or more wide area network (WAN) memory devices.

13. A memory controller comprises:

an input unit operable to receive a memory access request regarding a data segment; and

a processing unit operable to:

maintain a memory map of memories of a computing device, wherein the memories include main memory, core memory, and non-core memory, wherein the memory map includes a plurality of column sections and a plurality of data type row sections;

interpret the memory access request to determine a data type of the data segment;

identify one of the plurality of data type row sections based on the data type of the data segment;

identify addresses within memory space of at least some of the plurality of column sections intersecting the one of the plurality of data type row sections for at least a decode threshold number of encoded data slices when the memory access request indicates that the data segment is dispersed storage error encoded; and

facilitating accessing the at least the decode threshold number of encoded data slices based on the addresses.

14. The memory controller of claim 13 , wherein the plurality of data type row sections comprises:

a kernel memory block;

a user memory block; and

an unused memory block.

15. The memory controller of claim 13 , wherein the processing unit is further operable to:

reprovision a portion of the unused memory block to the kernel memory block or to the user memory block.

16. The memory controller of claim 13 , wherein the processing unit is further operable to:

when the memory access request is a write request, facilitating the accessing of the at least the decode threshold number of encoded data slices by:

sending the data segment to a dispersed storage processing module that is operable to encode the data segment into a set of encoded data slices using an error encoding dispersal function; and

sending an encoded data slice of the set of encoded data slices to a corresponding one of the plurality of column sections for storage therein.

17. The memory controller of claim 13 , wherein the processing unit is further operable to:

interpret the memory access request to determine an operating system data type of the data segment, wherein the operating system data type includes an operating system application, one or more operating system level drivers, and one or more operating system level application program interfaces (API); and

identify a kernel row section as the one of the plurality of data type row sections.

18. The memory controller of claim 13 , wherein the processing unit is further operable to:

interpret the memory access request to determine an user data type of the data segment, wherein the user data type includes user applications, user level drivers, and user level application program interfaces (API); and

identify a user data row section as the one of the plurality of data type row sections.