Apparatus for dedicated hardware and software split implementation of rate matching and de-matching

1. An apparatus for rate de-matching, comprising:

a processor calculating at least one rate de-matching parameter for data;

a controller receiving the at least one rate de-matching parameter and preparing setup parameters for a state machine circuit;

the state machine circuit receiving the calculated rate de-matching parameters from the controller and configured to control a selector based on the calculated rate de-matching parameters; and

the selector receiving a data selection signal from the state machine and configured to output one of a zero value, output from a bit clamp, and a puncture/replace bit based on the data selection signal.

2. The apparatus of claim 1 , further including:

a memory for storing the at least one rate de-matching parameter.

3. The apparatus of claim 1 , further including:

a first interleaver receiving output data and signaling from a first buffer; and

a second interleaver inputting data and signaling to a second buffer.

4. The apparatus of claim 1 , further including:

a latch latching output from an accumulator and configured to reset in response to a reset signal from the state machine circuit;

the accumulator adding the latch output with input data and outputting an accumulated value; and

the bit clamp clamping the number of bits representing the accumulated value to a preset number of bits.