IP Library Granted Patent US 9,159,703
Granted Patent B2
US 9,159,703 · App. 14/023,038 · Granted Oct 13, 2015

Power converter package including vertically stacked driver IC

Inventors: Eung San Cho (Torrance, CA); Andrew N. Sawle (East Grinstead, GB); Mark Pavier (Felbridge, GB); Daniel Cutler (Betchworth, GB)
Assignee: International Rectifier Corporation
H01L25/0652H01L21/4825H01L21/561H01L23/3121H01L23/49562H01L23/49575H01L24/24H01L24/25H01L24/73H01L24/82H01L25/072H01L25/117H01L25/16H01L24/16H01L24/32H01L24/85H01L2224/16225H01L2224/24245H01L2224/32225H01L2224/32245H01L2224/48091H01L2224/48145H01L2224/73227H01L2224/73265H01L2224/73267H01L2924/00014H01L2924/13091
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Quick Facts
Patent No.
US 9,159,703
App. No.
14/023,038
Granted
Oct 13, 2015
Kind
B2
Abstract

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.

Claims (22)

1. A semiconductor package comprising:

a control conductive carrier having a die side and an opposite input/output (I/O) side connecting said semiconductor package to a mounting surface;

a control FET of a power converter switching stage attached to said die side of said control conductive carrier;

a driver integrated circuit (IC) for driving said control FET, said driver IC situated above said control FET and electrically coupled to said control FET by at least one conductive buildup layer formed over said control conductive carrier.

2. The semiconductor package of claim 1 , further comprising a sync conductive carrier having another die side and another opposite input/output (I/O) side connecting said semiconductor package to said mounting surface;

a sync FET of said power converter switching stage attached to said another die side of said sync conductive carrier.

3. The semiconductor package of claim 1 , wherein said driver IC is electrically coupled to said at least one conductive buildup layer formed over said control conductive carrier by bondwire.

4. The semiconductor package of claim 1 , wherein said driver IC is flip chip mounted above said at least one conductive buildup layer formed over said control conductive carrier.

5. The semiconductor package of claim 1 , wherein said control FET comprises a silicon FET.

6. The semiconductor package of claim 1 , wherein said control FET comprises a III-Nitride FET.

7. The semiconductor package of claim 1 , wherein said power converter switching stage is implemented as part of a buck converter.

8. A semiconductor package comprising:

a sync conductive carrier having a die side and an opposite input/output (I/O) side connecting said semiconductor package to a mounting surface;

a sync FET of a power converter switching stage attached to said die side of said sync conductive carrier;

a driver integrated circuit (IC) for driving said sync FET, said driver IC situated above said sync FET and electrically coupled to said sync FET by at least one conductive buildup layer formed over said sync conductive carrier.

9. The semiconductor package of claim 8 , further comprising a control conductive carrier having another die side and another opposite input/output (I/O) side connecting said semiconductor package to said mounting surface;

a control FET of said power converter switching stage attached to said another die side of said control conductive carrier.

10. The semiconductor package of claim 8 , wherein said driver IC is electrically coupled to said at least one conductive buildup layer formed over said sync conductive carrier by bondwire.

11. The semiconductor package of claim 8 , wherein said driver IC is flip chip mounted above said at least one conductive buildup layer formed over said sync conductive carrier.

12. The semiconductor package of claim 8 , wherein said sync FET comprises a silicon FET.

13. The semiconductor package of claim 8 , wherein said sync FET comprises a III-Nitride FET.

14. The semiconductor package of claim 8 , wherein said power converter switching stage is implemented as part of a buck converter.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Feb 29, 2016
From: INTERNATIONAL RECTIFIER CORPORATION; INFINEON TECHNOLOGIES AMERICAS CORP.
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 037854/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2013
From: CHO, EUNG SAN; SAWLE, ANDREW N.; PAVIER, MARK; CUTLER, DANIEL
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 031177/0368 →
Continuity (2)
Provisional Application 61715749 · Oct 18, 2012
Related Publication 20140110863A1 · Apr 24, 2014