Granted Patent B1

US 8,810,263 · App. 14/023,083 · Granted Aug 19, 2014

Abstract

Claims (33)

1. An apparatus comprising:

an input node coupled to a capacitance sense pin coupled to an electrode of a sense array;

a capacitance-sensing circuit coupled to the input node, wherein the capacitance-sensing circuit comprises:

a signal generator coupled to a second capacitance sense pin coupled to a second electrode of the sense array;

an integrator configured to measure a first mutual capacitance of an intersection between the electrode and the second electrode with a first resolution;

a first integrator capacitor coupled between the input node and an output of the integrator; and

an adaptive resolution circuit coupled to the capacitance-sensing circuit and the input node, wherein the adaptive resolution circuit is configured to selectively modify an integration parameter to set the integrator to measure a second mutual capacitance of the intersection with a second resolution, wherein the integration parameter is an integration capacitance of the integrator, and wherein the adaptive resolution circuit comprises:

a second capacitor;

a comparator coupled to the output of the integrator; and

a switch coupled to an output of the comparator, wherein the comparator is to selectively switch the second capacitor in parallel to the first integrator capacitor of the capacitance-sensing circuit to modify the integration capacitance of the integrator for the second resolution.

2. The apparatus of claim 1 , wherein the capacitance-sensing circuit comprises an analog-to-digital converter (ADC) coupled to the output of the integrator to convert the output of the integrator to a digital value.

3. A method comprising:

driving a transmit (TX) signal on a first capacitance sense pin coupled to a first electrode of a sense array;

receiving at an input node of a capacitance-sensing circuit a receive (RX) signal on a second capacitance sense pin coupled to a second electrode of the sense array;

integrating the RX signal by an integrator comprising a first integrator capacitor with a first resolution of the capacitance-sensing circuit, wherein the first integrator capacitor is coupled between the input node and an output of the integrator, wherein the integrated RX signal with the first resolution represents a first mutual capacitance between the first electrode and the second electrode;

selectively coupling a second capacitor in parallel to the first integrator capacitor to modify the integrator to integrate with a second resolution of the capacitance-sensing circuit, wherein the selectively coupling comprises:

comparing the output of the integrator with a comparator; and

selectively coupling the second capacitor in parallel to the integrator capacitor via a switch to modify the integration capacitance for the second resolution based on an output of the comparator; and

integrating the RX signal by the integrator with the second resolution, wherein the integrated RX signal with the second resolution represents a second mutual capacitance between the first electrode and the second electrode.

4. The method of claim 3 , further comprising converting the output of the integrator to a digital value by an analog-to-digital converter (ADC) coupled to the output of the integrator.

5. A system comprising:

a sense array comprising a plurality of electrodes; and

a processing device coupled to the sense array via capacitance sense pins, wherein the processing device comprises:

an input node coupled to a first pin of the capacitance sense pins;

a signal generator coupled to a second pin of the capacitance sense pins;

an integrator coupled to the input node and to measure a mutual capacitance of an intersection between a pair of electrodes of the sense array, the pair being coupled to the first pin and the second pin;

a first integrator capacitor coupled between the input node and an output of the integrator; and

an adaptive resolution circuit coupled to the input node and the output of the integrator, wherein the adaptive resolution circuit comprises:

a second integrator capacitor;

a comparator coupled to the output of the integrator; and

a switch coupled to an output of the comparator, wherein the comparator is to selectively switch the second integrator capacitor in parallel to the first integrator capacitor of the, wherein the integrator is to measure the mutual capacitance with a first resolution when the second integrator capacitor is not switched in parallel to the first integrator capacitor and to measure the mutual capacitance with a second resolution when the integrator capacitor is switched in parallel to the first integrator capacitor.

6. The system of claim 5 , wherein the processing device comprises a multiplexer bus coupled to the input node of the integrator, wherein the multiplexer is to selectively couple the input node to one of the capacitance sense pins.

7. The system of claim 5 , wherein the processing device further comprises an analog-to-digital converter (ADC) coupled to the output of the integrator to convert the output of the integrator to a digital value.

Assignments (6)