Memory controller and memory system
A memory controller having a plurality of channels according to an embodiment of the present invention includes: a valid page information management unit that manages, for each of the channel, identification information of a valid page; a write buffer that stores data to be written to the memory; a garbage collection control unit that executes a garbage collection process; and a channel controller capable of executing multi-plane read. The garbage collection control unit controls multi-plane read of the channel controller based on the identification information to level a total number of valid pages read from each of the channel.
1. A memory controller having a plurality of channels connectable to a plurality of nonvolatile memories, comprising:
a valid page information management unit configured to manage identification information corresponding to at least one valid page of the nonvolatile memories, the at least one valid page being physical page of the nonvolatile memories storing valid data;
a write buffer configured to store data to be written to the nonvolatile memories;
a garbage collection control unit configured to execute a garbage collection process, which includes transferring the valid data of the at least one valid page into the write buffer and writing the valid data back to the nonvolatile memories; and
a channel controller, provided in each of the channels, configured to execute a multi-plane read to the nonvolatile memories, the multi-plane read including reading valid data stored in a plurality of the at least one physical page included in multiple parallel-operable planes of the nonvolatile memories,
wherein the garbage collection control unit is further configured to control the executed multi-plane read of the channel controller in each of the channels based on the identification information so that a total number of valid pages read for each channel of the plurality of channels is constant.
2. The memory controller according to claim 1 , wherein
the identification information is a physical address of the at least one valid page, and
the garbage collection control unit is further configured to execute the multi-plane read of the valid data stored in the at least one valid page in the order in which the physical address is stored in the valid page information management unit.
3. The memory controller according to claim 1 , wherein an upper-limit number of multi-plane reads for each of the channels is provided.
4. The memory controller according to claim 3 , further comprising a scheduler, wherein
the identification information is assigned to a group of a plurality of physical pages that is readable in parallel in the multi-plane read,
the valid page information management unit includes a plurality of queues provided in each of the channels, the plurality of queues maintaining a number of items of identification information corresponding to the number of valid pages included in the group of the plurality of readable physical pages, and
the scheduler determines a combination of the items of identification information, for which the multi-plane read is to be executed, based on the information maintained in the valid page information management unit.
5. The memory controller according to claim 4 , wherein the scheduler is configured to determine a combination of the items of identification information based on a queueing state of the identification information in the queue among predetermined combination candidates.
6. The memory controller according to claim 5 , wherein the combination candidates are determined such that the total number of valid pages has a predetermined value.
7. The memory controller according to claim 1 , wherein the valid page information management unit is further configured to maintain the identification information based on logs in which the logical address of the data written to the at least one physical page is recorded in a time-series order.
8. The memory controller according to claim 2 , wherein the valid page information management unit is further configured to maintain the identification information based on logs in which the logical address of the data written to the at least one physical page is recorded in a time-series order.
9. The memory controller according to claim 3 , wherein the valid page information management unit is further configured to maintain the identification information based on logs in which the logical address of the data written to the at least one physical page is recorded in a time-series order.
10. The memory controller according to claim 4 , wherein the valid page information management unit is further configured to maintain the identification information based on logs in which the logical address of the data written to the at least one physical page is recorded in a time-series order.
11. A memory system comprising:
a plurality of nonvolatile memories provided in each of a plurality of channels;
a valid page information management unit configured to manage identification information corresponding to at least one valid page of the nonvolatile memories, the at least one valid page being at least one physical page of the nonvolatile memories storing valid data;
a write buffer configured to store data to be written to the nonvolatile memories;
a garbage collection control unit configured to execute a garbage collection process, which includes transferring the valid data of the at least one valid page into the write buffer and writing the valid data back to the nonvolatile memories; and
a channel controller, provided in each of the channels, configured to execute multi-plane read to the nonvolatile memories, the multi-plane read including reading valid data stored in a plurality of the at least one physical page included in multiple parallel-operable planes of the nonvolatile memories,
wherein the garbage collection control unit is further configured to control the executed multi-plane read of the channel controller in each of the channels based on the identification information so that a total number of valid pages read for each channel of the plurality of channels is constant.
12. The memory system according to claim 11 , wherein
the identification information is a physical address of the at least one valid page, and
the garbage collection control unit is further configured to execute the multi-plane read of the valid data stored in the at least one valid page in the order in which the physical address is stored in the valid page information management unit.
13. The memory system according to claim 11 , wherein an upper-limit number of multi-plane reads for each of the channels is provided.
14. The memory system according to claim 13 , further comprising a scheduler, wherein
the identification information is assigned to a group of a plurality of physical pages that is readable in parallel in the multi-plane read,
the valid page information management unit includes a plurality of queues provided in each of the channels, the plurality of queues maintaining a number of items of identification information corresponding to the number of valid pages included in the group of the plurality of readable physical pages, and
the scheduler determines a combination of the items of identification information, for which the multi-plane read is to be executed, based on the information maintained in the valid page information management unit.
15. The memory system according to claim 14 , wherein the scheduler is configured to determine a combination of the items of identification information based on a queueing state of the identification information in the queue among predetermined combination candidates.
16. The memory system according to claim 15 , wherein the combination candidates are determined such that the total number of valid pages has a predetermined value.
17. The memory system according to claim 11 , wherein the valid page information management unit is further configured to maintain the identification information based on logs in which the logical address of the data written to the at least one physical page is recorded in a time-series order.
18. The memory system according to claim 12 , wherein the valid page information management unit is further configured to maintain the identification information based on logs in which the logical address of the data written to the at least one physical page is recorded in a time-series order.
19. The memory system according to claim 13 , wherein the valid page information management unit is further configured to maintain the identification information based on logs in which the logical address of the data written to the at least one physical page is recorded in a time-series order.
20. The memory system according to claim 14 , wherein the valid page information management unit is further configured to maintain the identification information based on logs in which the logical address of the data written to the at least one physical page is recorded in a time-series order.