IP Library Granted Patent US 9,330,787
Granted Patent B2
US 9,330,787 · App. 14/023,890 · Granted May 3, 2016

Memory system and memory controller

Inventor: Gen Ohshima (Tokyo, JP)
Assignee: Kabushiki Kaisha Toshiba
G11C29/42G06F3/0619G06F11/1068G06F11/1412G06F12/02G06F2212/7211G11C16/0483G11C16/34G11C16/3418G11C16/3431G11C29/28G11C2029/0409G11C2029/0411
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Quick Facts
Patent No.
US 9,330,787
App. No.
14/023,890
Granted
May 3, 2016
Kind
B2
Abstract

According to one embodiment, a memory system includes a non-volatile memory and a memory controller that controls the non-volatile memory. The non-volatile memory includes a memory cell array and an access control unit. The access control unit performs a program operation for changing threshold voltages of memory cells and a read operation for reading data from the memory cells. The memory controller includes a read/write control unit having a first program parameter set and a second program parameter set. The read/write control unit causes the access control unit to perform a program operation based on the first program parameter set, and when a predetermined condition is satisfied, performs switching from the first program parameter set to the second program parameter set and causes the access control unit to perform a program operation based on the second program parameter set.

Claims (47)

1. A memory system comprising:

a non-volatile memory; and

a memory controller that controls the non-volatile memory, wherein

the non-volatile memory comprises:

a memory cell array that includes a plurality of memory cells which are configured to be settable with a plurality of different threshold voltages and to store data corresponding to the threshold voltages set thereto, each of the plurality of the different threshold voltages of the memory cells forming each of a plurality of different distributions, and

an access control unit that performs a program operation for programing data to the memory cells and a read operation for reading data from the memory cells, wherein

the memory controller comprises:

a read/write control unit that causes the access control unit to perform a program operation based on a first program parameter set, performs switching from the first program parameter set to a second program parameter set when the memory system starts to be used, and when a predetermined condition is satisfied, and causes the access control unit to perform a program operation based on the second program parameter set, a difference between a threshold voltage of a highest distribution and a threshold voltage of a lowest distribution set to the memory cells by the program operation based on the second program parameter set is larger than a difference between a threshold voltage of a highest distribution and a threshold voltage of a lowest distribution set to the memory cells by the program operation based on the first program parameter set, wherein

the read/write control unit causes the access control unit to perform a read operation based on a first read parameter set when the read/write control unit causes the access control unit to perform the program operation based on the first program parameter set, and causes the access control unit to perform a read operation based on a second read parameter set when the read/write control unit causes the access control unit to perform the program operation based on the second program parameter set, the first read parameter set corresponding to the first program parameter set, and the second read parameter set corresponding to the second program parameter set.

2. The memory system according to claim 1 ,

wherein the memory controller further includes an error correcting unit which performs an error correction process on data read from the non-volatile memory, and

the read/write control unit performs the switching when an error bit rate of data read from the non-volatile memory exceeds a predetermined threshold value.

3. The memory system according to claim 1 ,

wherein the read/write control unit performs the switching in units of blocks of the non-volatile memory, a block being an erase unit of the non-volatile memory.

4. The memory system according to claim 3 ,

wherein the read/write control unit sequentially performs an error correction process on data stored in a plurality of blocks included in the non-volatile memory, and performs switching for a block which storing data of which error bit rate exceeds a predetermined threshold value.

5. The memory system according to claim 1 ,

wherein the memory controller further includes a count unit that counts at least one of the number of erase operation times, the number of read operation times, and the number of program operation times of the memory cell, and

the read/write control unit performs the switching with reference to at least one of the number of erasing times, the number of reading times, and the number of writing times.

6. The memory system according to claim 5 ,

wherein the read/write control unit performs the switching by sequentially reference to the number of erasing times of a plurality of blocks included in the non-volatile memory, and performs the switching.

7. A memory system comprising:

a non-volatile memory; and

a memory controller that controls the non-volatile memory, wherein

the non-volatile memory comprises:

a memory cell array that includes a plurality of memory cells which are configured to be settable with a plurality of different threshold voltages and to store data corresponding to the threshold voltages set thereto, each of the plurality of the different threshold voltages of the memory cells forming each of a plurality of different distributions, and

an access control unit that performs a program operation for programing data to the memory cells and a read operation for reading data from the memory cells, wherein

the memory controller causes the access control unit to perform a program operation in a first mode when the memory system starts to be used, and when a predetermined condition is satisfied, performs switching from the first mode to a second mode and causes the access control unit to perform a program operation in the second mode,

a difference between a threshold voltage of a highest distribution and a threshold voltage of a lowest distribution set to the memory cell by the program operation in the second mode is larger than a difference between a threshold voltage of a highest distribution and a threshold voltage of a lowest distribution set to the memory cell by the program operation in the first mode, and

the memory controller causes the access control unit to perform a read operation in a third mode when the memory controller causes the access control unit to perform the program operation in the first mode, and causes the access control unit to perform a read operation in a fourth mode when the memory controller causes the access control unit to perform the program operation in the second mode, the third mode corresponding to the first mode, and the fourth mode corresponding to the second mode.

8. The system according to claim 7 ,

wherein the memory controller further includes an error correcting unit which performs an error correction process on data read from the non-volatile memory, and

the read/write control unit performs the switching when an error bit rate of data read from the non-volatile memory exceeds a predetermined threshold value.

9. The system according to claim 7 ,

wherein the memory controller further includes a count unit that counts at least one of the number of erase operation times, the number of read operation times, and the number of program operation times of the memory cell, and

the read/write control unit performs the switching with reference to at least one of the number of erasing times, the number of reading times, and the number of writing times.

10. A memory system comprising:

a non-volatile memory; and

a memory controller that controls the non-volatile memory, wherein

the non-volatile memory comprises:

a memory cell array that includes a plurality of memory cells which are configured to be settable with a plurality of different threshold voltages and to store data corresponding to the threshold voltages set thereto, each of the plurality of the different threshold voltages of the memory cells forming each of a plurality of different distributions, and

an access control unit that performs a program operation for programing data to the memory cells and a read operation for reading data from the memory cells, wherein

the memory controller comprises:

a read/write control unit that causes the access control unit to perform a program operation based on a first program parameter set when the memory system starts to be used, controls changing the first program parameter set to a second program parameter set when a predetermined time elapses, and causes the access control unit to perform a program operation based on the second program parameter set, a difference between a threshold voltage of a highest distribution and a threshold voltage of a lowest distribution set to the memory cells by the program operation based on the second program parameter set being larger than a difference between a threshold voltage of a highest distribution and a threshold voltage of a lowest distribution set to the memory cells by the program operation based on the first program parameter set, and wherein

the read/write control unit causes the access control unit to perform a read operation based on a first read parameter set when the read/write control unit causes the access control unit to perform the program operation based on the first program parameter set, and causes the access control unit to perform a read operation based on a second read parameter set when the read/write control unit causes the access control unit to perform the program operation based on the second program parameter set, the first read parameter set corresponding to the first program parameter set, and the second read parameter set corresponding to the second program parameter set.

11. The memory system according to claim 10 ,

wherein the read/write control unit controls the changing in units of blocks of the non-volatile memory, a block being an erase unit of the non-volatile memory.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2013
From: OHSHIMA, GEN
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 031810/0680 →
Continuity (2)
Provisional Application 61802832 · Mar 18, 2013
Related Publication 20140281769A1 · Sep 18, 2014