Storage device and storage method

1. A storage device comprising:

a plurality of memory nodes, each of which includes a storage unit including a plurality of storage areas, each of the plurality of storage areas having a predetermined size, each of the plurality of memory nodes being arranged at a lattice point of a lattice, each of the plurality of memory nodes including input ports and output ports, and each of the plurality of memory nodes being connected, through an input port and output port, to each of one or more adjacent memory nodes among the plurality of memory nodes,

the plurality of memory nodes constituting three or more groups, each of the three or more groups including two or more memory nodes, each of the plurality of memory nodes being included in any one group among the three or more groups, and each of the plurality of memory nodes being connected to all other memory nodes in the same group directly or via one or more memory nodes in the same group; and

a control unit that is connected to a first memory node that is one of the plurality of memory nodes, the control unit being configured to

divide data received from an external computer to generate three or more data pieces each having a predetermined size, the data being indicated by a logical address,

generate parity from the three or more data pieces,

allocate each of writing destinations of the three or more data pieces and the parity in a different group among the three or more groups,

generate packets each addressed to a different destination among the writing destinations, the packets each including a corresponding data piece among the three or more data pieces and the parity, and

transmit the packets to the first memory node, wherein

when a memory node receives a packet among the transmitted packets through an input port of the memory node,

in a case where the received packet is not addressed to the memory node itself, the memory node transmits the received packet to one of memory nodes that are adjacent to the memory node through an output port of the memory node, and

in a case where the received packet is addressed to the memory node itself, the memory node performs storing the data piece included in the received packet into a storage unit included in the memory node.

2. The storage device according to claim 1 , wherein,

in a case where a cycle of allocation of the writing destinations to the plurality of storage areas corresponding to each other in the plurality of memory nodes is completed, the control unit is further configured to change the group of the writing destinations of the parities.

3. The storage device according to claim 1 , wherein

the control unit is further configured to sequentially allocate the writing destinations of the parities to the three or more groups.

4. The storage device according to claim 1 , wherein

the control unit is further configured to divide the plurality of memory nodes in two or more directions to generate the three or more groups.

5. The storage device according to claim 1 , wherein one of the plurality of memory nodes further includes a detector configured to detect an error bit included in data read from the storage unit and add a result of the detection to a result corresponding to at least one of a reading command and a writing command transmitted from the control unit to transmit the added result to the control unit.

6. The storage device according to claim 1 , wherein,

when a memory node among the plurality of memory nodes receives a packet among the packets, the memory node determines whether the received packet is addressed to the memory node itself,

in a case where the received packet is addressed to the memory node itself, the memory node performs writing of the data piece included in the received packet, and,

in a case where the received packet is not addressed to the memory node itself, the memory node transmits the received packet to one of memory nodes that are adjacent to the memory node.

7. The storage device according to claim 1 , wherein

each of the writing destinations of the three or more data pieces is indicated by a combination of a first address which indicates a memory node and a second address which indicate a storage area, and

the control unit determines, based on the logical address, the combination of the first address and the second address for each of the three or more data pieces.