Display control device and mobile electronic apparatus

1. A display control driver on a semiconductor substrate, comprising:

a memory configured to store display data to be displayed on a display panel, the memory comprising

a plurality of memory cells arranged in row and column directions;

a plurality of word lines to each of which a number of memory cells in a same row are coupled; and

a plurality of bit lines arranged in a direction crossing the word lines and to which input nodes and output nodes are connected;

a drive circuit configured to provide drive signals to the display panel according to data read from the memory;

a first data holding circuit configured to hold the display data and configured to receive the display data in units of a number of bits and to hold the display data;

a second data holding circuit coupled to the first data holding circuit and configured to receive and hold the display data supplied from the first data holding circuit;

a control register configured to store a value for deciding a writing mode of the second data holding circuit and the memory, the writing mode including a consecutive writing mode and a collective writing mode; and

a transfer circuit coupled between the second data holding circuit and the memory,

wherein the transfer circuit is configured to transfer the display data from the second holding circuit to at least a part of the input nodes of the memory specified by the value stored in the control register based on a writing mode,

wherein, in the consecutive writing mode, the display data is transferred from the first data holding circuit to the second data holding circuit in units of the number of bits consecutively, and the transfer circuit transfers the display data from the second data holding circuit is transferred to the memory in units of the number of bits consecutively, and

wherein, in the collective writing mode, the display data is transferred from the first data holding circuit to the second data holding circuit in units of n times the number of bits collectively, where n is an integer larger than 1, the transfer circuit transfers the display data from the second data holding circuit to memory cells coupled to a same word line of the memory in units of n times the number of bits collectively, and the display data is successively transferred to the first data holding circuit during a same time period in which the display data is transferred from the first data holding circuit to the second data holding circuit collectively.

2. The display control device according to claim 1 , further comprising:

a plurality of first external terminals to which the display data in units of a number of bits to be stored in the memory is to be supplied; and

a plurality of second external terminals coupled to outputs of the drive circuit and configured to output the drive signals to the display panel,

wherein the first data holding circuit has a plurality of first latch circuits each of which is configured to hold the display data by storing the display data supplied from the first external terminals, in units of the number of bits; and

wherein the second data holding circuit has a plurality of second latch circuits each of which is coupled to a corresponding one of said first latch circuits and is configured to hold the display data received from the corresponding first latch circuit.

3. The display control device according to claim 2 ,

wherein, in the consecutive writing mode, one of the first latch circuit and the corresponding second latch circuit hold therein first display data in units of the number of bits, and thereafter the first display data is written into the memory before another of the first latch circuits and the corresponding second latch circuit hold therein consecutive second display data in units of the number of bits, and

wherein, in the collective writing mode, one of the first latch circuits hold a plurality of first display data in units of the number of bits in sequence, and thereafter said one first latch circuits outputs the plurality of first display data in units of n times the number of bits into corresponding ones of said second latch circuits, and thereafter said corresponding second latch circuits provide the plurality of first display data to the memory to write the plurality of first display data in units of n times the number of bits into the memory, collectively, while a plurality of second display data, that follows the plurality of first display data, in units of the number of bits is written into other ones of the first latch circuits in sequence.

4. The display control device according to claim 1 , further comprising:

a gradation voltage generation circuit which generates gradation voltages; and

a gradation voltage select circuit which selects a desired gradation voltage suitable for the display data that is read from the memory.

5. The display control device according to claim 1 , wherein the memory stores the display data in a bit map system.

6. The display control device according to claim 1 ,

wherein the first data holding circuit includes a plurality of latch circuits, and

wherein the number of latch circuits is equal to a number of memory cells coupled to one word line of the memory.

7. The display control device according to claim 1 ,

wherein the number of bits of the display data is 16 bits, and n is 4.

8. The display control device according to claim 1 , further comprising:

a third data holding circuit coupled to the memory and configured to receive and hold the display data read from the memory; and

a bit operation circuit coupled between the third data holding circuit and the first data holding circuit,

wherein the bit operation circuit is configured to perform logical operations for the display data to be received for the first data holding circuit using the display data supplied by the third data holding circuit, and stores the logical operation result to the first data holding circuit.

9. The display control device according to claim 1 , further comprising:

an address counter which generates addresses for the memory.

10. The display control device according to claim 1 , further comprising:

a clock generating circuit which generates clock pulses; and

a timing generator which is coupled to the clock generating circuit.

11. The display control device according to claim 1 , wherein n is 4.