High speed level shifter with amplitude servo loop
A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.
1. A circuit comprising:
a supply input configured to provide a target high output level;
a signal input configured to carry an input signal;
a signal output configured to carry an output signal; and
level translation circuitry configured to generate the output signal by shifting the input signal between a target low output level and the target high output level, the level translation circuitry comprising:
an amplitude control circuit coupled to the supply input and the signal output;
an overvoltage protection circuit in series with the amplitude control circuit;
a current bleed circuit coupled to the overvoltage protection circuit, the current bleed circuit configured to drain current from the overvoltage protection circuit; and
a switching circuit in series with the overvoltage protection circuit and coupled to the signal input.
2. The circuit of claim 1 , where:
the amplitude control circuit comprises an amplitude control transistor.
3. The circuit of claim 1 , where:
the overvoltage protection circuit comprises a cascode coupled transistor in series with the amplitude control circuit and the switching circuit.
4. The circuit of claim 1 , where:
the amplitude control circuit comprises an amplitude control transistor;
the amplitude control transistor comprises a gate; and where:
the gate is coupled to an amplitude control gate voltage.
5. The circuit of claim 4 , further comprising:
a feedback loop configured to provide the amplitude control gate voltage.
6. The circuit of claim 5 , where the feedback loop comprises:
a reference voltage input;
a feedback voltage input coupled to the signal output; and
a voltage control circuit configured to generate the amplitude control gate voltage responsive to the reference voltage input in comparison to the feedback voltage input.
7. The circuit of claim 1 , where:
the overvoltage protection circuit comprises a cascode coupled transistor in series with the amplitude control circuit and the switching circuit.
8. The circuit of claim 7 , where the current bleed circuit is configured to prevent the cascode coupled transistor from completely turning off.
9. The circuit of claim 8 , where the current bleed circuit comprises a diode coupled transistor.
10. The circuit of claim 7 , where the current bleed circuit is configured to allow a current to flow through the cascode coupled transistor.
11. The circuit of claim 7 , further comprising a voltage control circuit configured to regulate the amplitude control circuit to prevent the target low level from falling below a preselected voltage.
12. A circuit comprising:
a signal input configured to carry an input signal characterized by a nominal high level and a nominal low level;
a signal output configured to carry an output signal;
level translation circuitry in communication with the signal input and the signal output and configured to translate the input signal to a shifted high level and a shifted low level in the output signal; and
a voltage control circuit comprising:
a feedback input configured to receive the signal output; and
a comparison circuit configured to:
compare the signal output to a preselected reference voltage; and
responsive to the comparison, prevent the shifted low level from falling below the preselected reference voltage.
13. The circuit of claim 12 , further comprising:
a switching circuit coupled to the signal input; and
an overvoltage protection circuit in series with the switching circuit.
14. The circuit of claim 13 , where:
the switching circuit is characterized by a voltage stress rule; and
the overvoltage protection circuit is configured keep voltage stress on the switching circuit compliant with the voltage stress rule.
15. The circuit of claim 14 , where the voltage stress rule comprises a gate-to-drain voltage limit, a gate-to-source voltage limit, or both.
16. The circuit of claim 12 , further comprising:
an amplitude control circuit regulated by the voltage control circuit.
17. The circuit of claim 16 , where the amplitude control circuit comprises a transistor with a gate regulated by the-voltage control circuit.
18. The circuit of claim 12 , where the comparison circuit comprises an error amplifier configured to drive the signal output at the feedback input to the preselected reference voltage.
19. A circuit comprising:
a supply input;
a signal input configured to carry an input signal characterized by a first convention high level and a first convention low level;
a signal output configured to carry an output signal;
level translation circuitry configured to translate the input signal between a shifted high level and a shifted low level compatible with a second convention in the output signal,
the level translation circuitry comprising:
an amplitude control transistor coupled between the supply input and the signal output;
an overvoltage protection transistor in series with the amplitude control transistor;
a current bleed circuit coupled to the overvoltage protection transistor, the current bleed circuit configured to prevent the overvoltage protection transistor from fully turning off; and
a switching transistor in series with the overvoltage protection transistor, the switching transistor coupled to the signal input; and
a voltage control circuit configured to regulate the amplitude control transistor to prevent the shifted low level from falling below a preselected voltage.
20. The circuit of claim 19 , where the voltage control circuit comprises:
a reference voltage input set to the preselected voltage;
a feedback voltage input coupled to the signal output; and
a difference amplifier coupled to the reference voltage input and the feedback voltage input,
where the difference amplifier is configured to regulate the amplitude control transistor responsive to a difference between the reference voltage input and the feedback voltage input.