IP Library Granted Patent US 9,383,967
Granted Patent B2
US 9,383,967 · App. 14/026,167 · Granted Jul 5, 2016

Accumulation of waveform data using alternating memory banks

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Quick Facts
Patent No.
US 9,383,967
App. No.
14/026,167
Granted
Jul 5, 2016
Kind
B2
Abstract

System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.

Claims (53)

1. A system for accumulating waveform data, the system comprising:

a digitizer, comprising:

a circuit;

a first memory bank, coupled to the circuit; and

a second memory bank, coupled to the circuit;

wherein the circuit is configured to:

a) store a first subset of the waveforms in the first memory bank;

b) accumulate each waveform of the first subset of waveforms in a chunk-wise manner, wherein each chunk has a specified size, thereby generating a first bank sum comprising a first partial accumulation of the set of waveforms;

c) store a second subset of waveforms in the second memory bank concurrently with b);

d) accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum comprising a second partial accumulation of the set of waveforms; and

wherein the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.

2. The system of claim 1 , wherein the circuit is further configured to:

e) accumulate the first and second bank sums into a running accumulation of the set of waveforms;

f) repeat a)-e) for successive further first and second subsets of the set of waveforms, thereby generating an accumulated record of the set of waveforms.

3. The system of claim 2 , wherein to perform e), the circuit is configured to:

store the bank sums in reserved space in the first and/or second memory banks;

wherein e) is performed using the reserved space.

4. The system of claim 1 , wherein the circuit is further configured to:

transfer the bank sums to a host computer using a host computer bus, and store the bank sums in host computer memory;

wherein the host computer is configured to:

e) accumulate the first and second bank sums into a running accumulation of the set of waveforms;

f) repeat a)-e) for successive further first and second subsets of the set of waveforms, thereby generating an accumulated record of the set of waveforms.

5. The system of claim 1 , wherein the circuit comprises a programmable hardware element.

6. The system of claim 5 , wherein the first and second memory banks are integrated into the programmable hardware element.

7. The system of claim 1 , wherein the circuit comprises an application specific integrated circuit (ASIC).

8. The system of claim 7 , wherein the first and second memory banks are integrated into the ASIC.

9. The system of claim 1 , wherein the first and second memory banks are integrated into the circuit.

10. The system of claim 1 , wherein the first and second memory banks are external to the circuit.

11. A hardware implemented method for accumulating waveform data, the method comprising:

a digitizer performing:

a) storing a first subset of the waveforms in a first memory bank of the digitizer;

b) accumulating each waveform of the first subset of waveforms in a chunk-wise manner, wherein each chunk has a specified size, thereby generating a first bank sum comprising a first partial accumulation of the set of waveforms;

c) concurrently with b), storing a second subset of waveforms in a second memory bank of the digitizer;

d) accumulating each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum comprising a second partial accumulation of the set of waveforms;

wherein the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.

12. The method of claim 11 , further comprising:

the digitizer performing:

e) accumulating the first and second bank sums into a running accumulation of the set of waveforms;

f) repeating a)-e) for successive further first and second subsets of the set of waveforms, thereby generating an accumulated record of the set of waveforms.

13. The method of claim 12 , further comprising:

the digitizer performing:

storing the bank sums in reserved space in the first and/or second memory banks;

wherein e) is performed using the reserved space.

14. The method of claim 11 , further comprising:

the digitizer performing:

transferring the bank sums to a host computer using a host computer bus and DMA, and storing the bank sums in host computer memory;

e) accumulating, via the host computer, the first and second bank sums into a running accumulation of the set of waveforms; and

f) repeating a)-e) for successive further first and second subsets of the set of waveforms, thereby generating an accumulated record of the set of waveforms.

15. The method of claim 11 , wherein a)-d) are performed by a circuit of the digitizer.

16. The method of claim 15 , wherein the circuit comprises a programmable hardware element.

17. The method of claim 15 , wherein the circuit comprises an application specific integrated circuit (ASIC).

18. The method of claim 15 , wherein the first and second memory banks are integrated into the circuit.

19. The method of claim 15 , wherein the first and second memory banks are external to the circuit.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 057280/0028) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 065231/0466 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 052935/0001) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
Reel/Frame 065653/0463 →
SECURITY INTEREST Recorded Jun 18, 2021
From: NATIONAL INSTRUMENTS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 057280/0028 →
SECURITY INTEREST Recorded Jun 14, 2020
From: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 052935/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2013
From: SALMON, ANITA L.; BERGERON, JEFF A.; THOMSON, ANDREW C.
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 031201/0546 →