Semiconductor pillar transistors having channels with different crystal orientations
According to an embodiment, a semiconductor device includes an underlying layer and a plurality of transistors. The underlying layer includes a first region and a second region provided adjacently to the first region. The transistors are arranged in a plane parallel to an upper surface of the underlying layer. Each transistor includes a channel allowing a current to flow in a first direction intersecting the plane. The plurality of transistors includes a first transistor provided on the first region and a second transistor provided on the second region, a first channel of the first transistor having a first crystal orientation, and a second channel of the second transistor having a second crystal orientation different from the first crystal orientation.
1. A semiconductor device, comprising:
an underlying layer including an insulator layer, and a metal layer provided on the insulator layer, the underlying layer including a first region and a second region; and
a plurality of transistors arranged in a plane parallel to an upper surface of the underlying layer, the plurality of transistors including a first transistor provided on the first region and a second transistor provided on the second region, each of the first and second transistors including a semiconductor pillar provided on the metal layer, the semiconductor pillar providing a channel allowing a current to flow in a first direction intersecting the plane,
a first channel of the first transistor having a first conductivity type and a first crystal orientation along the first direction; a second channel of the second transistor having the first conductivity type and a second crystal orientation along the first direction; and the second crystal orientation being different from the first crystal orientation.
2. The device according to claim 1 , wherein a length of the first region in a second direction parallel to the plane is not less than 10 times a length of the channel of each transistor in the first direction.
3. The device according to claim 1 , wherein
the channel of each transistor has a side surface along the first direction, and
each transistor includes:
a gate electrode facing the side surface; and
a gate insulating film provided between the gate electrode and the side surface.
4. The device according to claim 1 , wherein the semiconductor pillar includes a source provided on the metal layer, the channel provided on the source, and a drain provided on the channel.
5. The device according to claim 1 , wherein the semiconductor pillar is a nanowire extending in the first direction.
6. The device according to claim 1 , further comprising a memory cell array including a plurality of memory cells,
wherein the transistors are disposed between the underlying layer and the memory cell array, and configured to control an operation of the plurality of memory cells.
7. The device according to claim 1 , wherein
the channel has a side surface along the first direction, and
each of the transistors includes:
a gate electrode facing the side surface;
a gate insulating film provided between the gate electrode and the side surface; and
a charge retaining layer provided between the gate electrode and the gate insulating film.