Low Power Control for Multiple Coherent Masters
Systems and methods are provided for efficiently managing power among system components. In an embodiment, a power manager receives information from subsystems and determines which subsystem components will require power to perform upcoming tasks. Based on this received information, the power manager can power on and power down individual subsystem components. Systems and methods according to embodiments of the present disclosure enable a cache of a subsystem to be powered on without requiring a power-up of every component of the subsystem. Thus, disclosed systems and methods enable a first subsystem to snoop into a cache of a second subsystem without requiring a full power-up of the second subsystem.
1 . A system, comprising:
a first subsystem, comprising:
a cache memory, and
a processor core configured to initiate sending a message indicating that the processor core has finished performing a task;
a cache coherency module (CCM) coupled to the cache memory; and
a power manager coupled to the first subsystem, wherein the power manager is configured to:
receive the message,
determine whether the processor core is needed to perform an additional task, and
in response to determining that the processor core is not needed to perform the additional task, initiate powering down of the processor core without powering down the cache memory.
2 . The system of claim 1 , wherein the first subsystem further comprises:
a switch coupled to the processor core, wherein the power manager is configured to initiate toggling of the switch to initiate powering down the processor core.
3 . The system of claim 1 , wherein the cache memory is partitioned into a plurality of portions, wherein the plurality of portions includes a first portion and a second portion, and wherein the power manager is further configured to:
initiate powering down of the first portion without powering down the second portion.
4 . The system of claim 1 , further comprising:
a second subsystem coupled to:
the power manager, and
the CCM.
5 . The system of claim 4 , wherein the second subsystem comprises:
a switching regulator;
a phase-locked loop (PLL) coupled to the switching regulator;
a second cache memory coupled to:
the switching regulator, and
the PLL;
a first switch coupled to the switching regulator;
a second processor core coupled to the first switch;
a second switch coupled to the switching regulator; and
a third processor core coupled to the second switch.
6 . The system of claim 1 , wherein the power manager comprises:
a first sub-power manager coupled to the first subsystem; and
a second sub-power manager coupled to the CCM.
7 . The system of claim 1 , wherein the power manager is further configured to:
in response to initiating the powering down of the processor core, determine whether the first subsystem is needed to perform the additional task; and
in response to determining that the first subsystem is not needed to perform the additional task, initiate powering down of the first subsystem.
8 . The system of claim 1 , wherein the power manager is further configured to:
in response to initiating the powering down of the first subsystem, determine whether the CCM is needed to perform the additional task; and
in response to determining that the CCM is not needed to perform the additional task, initiate powering down of the CCM.
9 . The system of claim 1 , wherein the power manager is further configured to:
receive a request to power on the cache memory; and
in response to receiving the request to power on the cache memory, initiate powering up the first subsystem.
10 . The system of claim 1 , wherein the power manager is further configured to:
receive a request to power on the processor core;
in response to receiving the request to power on the processor core, determine whether the first subsystem is powered on;
in response to determining that the first subsystem is powered on:
initiate powering up the processor core; and
in response to determining that the first subsystem is not powered on:
initiate powering up the first subsystem, and
initiate powering up the processor core.
11 . The system of claim 1 , wherein the CCM is configured to:
receive a request to access data;
determine whether the data is stored in the cache memory;
in response to determining that the data is not stored in the cache memory, access data from external memory; and
in response to determining that the data is stored in the cache memory, initiate accessing the data.
12 . The system of claim 11 , wherein the CCM is further configured to:
determine whether the cache memory is powered on; and
in response to determining that the cache memory is not powered on, initiate sending a request to the power manager to power on the cache memory.
13 . The system of claim 11 , further comprising:
a second subsystem, comprising a second cache memory coupled to the CCM, wherein the CCM is further configured to:
determine whether the data is stored in the second cache memory.
14 . The system of claim 13 , wherein the CCM is further configured to:
determine whether at least a portion of the second cache memory is powered on; and
in response to determining that at least a portion of the second cache memory is not powered on, initiate sending a request to the power manager to power on at least a portion of the second cache memory.
15 . A system, comprising:
a first subsystem, comprising:
a first subsystem component configured to send a message indicating that the first subsystem component has finished performing a task, and
a second subsystem component;
a power manager coupled to the first subsystem, wherein the power manager is configured to:
receive the message,
determine whether the first subsystem component is needed to perform an additional task, and
in response to determining that the first subsystem component is not needed to perform the additional task, initiate powering down of the first subsystem component without powering down the second subsystem component.
16 . The system of claim 15 , wherein the first subsystem component is a processor core.
17 . The system of claim 15 , further comprising:
a cache coherency module (CCM) coupled to the second subsystem component, wherein the second subsystem component is a cache memory.
18 . A method, comprising:
receiving, using a power managing device, a request to power down a first component of a first subsystem;
determining, using the power managing device, whether the first component is needed to perform a task for a second subsystem; and
in response to determining that the first component is not needed to perform the task for the second subsystem, initiating, using the power managing device, powering down the first component without powering down a cache memory of the first subsystem.
19 . The method of claim 18 , further comprising:
determining whether the cache memory is needed to perform the task; and
in response to determining that the cache memory is not needed to perform the task, initiating powering down the first subsystem.
20 . The method of claim 19 , further comprising:
determining whether the second subsystem is needed to perform a second task; and
in response to determining that the second subsystem is not needed to perform the second task, initiating powering down the second subsystem.