SEMICONDUCTOR DEVICE
To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
1 . A semiconductor device comprising a semiconductor chip in the form of a rectangle having a first short side, a second short side in opposition to the first short side, a first long side, and a second long side in opposition to the first long side: wherein
the semiconductor chip includes:
first bump electrodes arranged along the first long side of the semiconductor chip and arranged at a position closer to the first long side than to the second long side in opposition to the first long side;
an internal circuit formed in the semiconductor chip; and
a first electrostatic protection circuit which protects the internal circuit against static electricity and is electrically coupled to the first bump electrode; wherein
the internal circuit is disposed at a position that overlaps the first bump electrode in a planar view; and wherein
the first electrostatic protection circuit is disposed at a position different from a position that overlaps the first bump electrode in a planar view.
2 . The semiconductor device according to claim 1 , wherein
the internal circuit is an SRAM.
3 . A semiconductor device comprising a semiconductor chip in the form of a rectangle having a first short side, a second short side in opposition to the first short side, a first long side, and a second long side in opposition to the first long side: wherein
the semiconductor chip includes:
first bump electrodes arranged along the first long side of the semiconductor chip and arranged at a position closer to the first long side than to the second long side in opposition to the first long side;
an internal circuit formed in the semiconductor chip; and
a first electrostatic protection circuit which protects the internal circuit against static electricity and is electrically coupled to the first bump electrode; wherein
the first electrostatic protection circuit is disposed at a position different from a position that overlaps the first bump electrode in a planar view; and wherein
a plurality of wirings passes at the position that overlaps the first bump electrode in a planar view.
4 . The semiconductor device according to claim 3 , having:
an element isolation region in which an insulating film is embedded in a groove in a semiconductor substrate; and
an active region and a dummy region that are regions defined in the element isolation region, wherein
the active region is a region where a semiconductor element is formed, and the dummy region is a region where the semiconductor element is not formed, and wherein
the dummy region is arranged at a position that overlaps the first bump electrode in a planar view.
5 . The semiconductor device according to claim 4 , wherein
the internal circuit is configured so as to include the semiconductor element formed in the active region.
6 . A semiconductor device comprising a semiconductor chip in the form of a rectangle having a pair of short sides and a pair of long sides: wherein
the semiconductor chip includes:
(a) a plurality of first bump electrodes arranged along a first long side of the semiconductor chip and arranged at a position closer to the first long side than to a second long side in opposition to the first long side;
(b) an internal circuit formed in the semiconductor chip; and
(c) a plurality of first electrostatic protection circuits which protect the internal circuit against static electricity and are electrically coupled to the first bump electrodes; and wherein
the first electrostatic protection circuits are arranged at a position different from a position that overlaps the first bump electrodes in a planar view.
7 . The semiconductor device according to claim 6 , wherein
in the lower layer of the first bump electrodes, the first electrostatic protection circuits are not arranged.