OS friendly microprocessor architecture

1. A microprocessor architecture for realizing efficient Operating System functions, and low power, comprising:

a program instruction memory module ( 102 I), said program instruction memory module having a first external cache and memory module ( 105 I), a first internal cache ( 110 I) a first DMA controller ( 122 I), and a first cache controller and cache bank module ( 126 I), said first external cache and memory module ( 105 I) connecting to said first internal cache ( 110 I) said first internal cache ( 110 I) connecting to said first DMA controller ( 122 I) and said first DMA controller ( 122 I) connecting to said first cache controller and cache bank module ( 126 I);

a data memory module ( 102 D), said data memory module having a second external cache and memory module ( 105 D), a second internal cache ( 110 D), a second DMA controller ( 122 D), and a second cache controller and cache bank module ( 126 D), said second external cache and memory module ( 105 D) connecting to said second internal cache ( 110 D), said second internal cache ( 110 D) connecting to said second DMA controller ( 122 D) and said second DMA controller ( 122 D) connecting to said second cache controller and cache bank module ( 126 D);

a register memory module ( 102 R), said register memory module having a third external cache and memory module ( 105 R), a third internal cache ( 110 R), a third DMA controller ( 122 R), and a third cache controller and cache bank module ( 126 D 126 R), said third external cache and memory module ( 105 R) connecting to said third internal cache ( 110 R), said third internal cache ( 110 R) connecting to said third DMA controller ( 122 R) and said third DMA controller ( 122 R) connecting to said third cache controller and cache bank module ( 126 R);

a pipeline state memory module ( 102 P), said pipeline state memory module having a fourth external cache and memory module ( 105 P), a fourth internal cache ( 110 P), a fourth DMA controller ( 132 ), and a fourth cache controller and cache bank module ( 136 ), said fourth external cache and memory module ( 105 P) connecting to said fourth internal cache ( 110 P), said fourth internal cache ( 110 P) connecting to said fourth DMA controller ( 132 ) and said fourth DMA controller ( 132 ) connecting to said fourth cache controller and cache bank module ( 136 ); and

a microprocessor pipeline ( 190 ), said microprocessor pipeline connecting to said first cache controller and cache bank module ( 126 I), to said second cache controller and cache bank module ( 126 D), to said third cache controller and cache bank module ( 126 R), and to said fourth cache controller and cache bank module ( 136 ); and wherein

said first DMA controller ( 122 I) and said first cache controller and cache bank module ( 126 I) communicate with said microprocessor pipeline for executing instructions while said first DMA controller ( 122 I) and said first cache controller and cache bank module ( 126 I) utilize said first internal cache ( 110 I) and first external cache and memory module ( 105 I) for memory storage;

said second DMA controller ( 122 D) and said second cache controller and cache bank module ( 126 D) communicate with said microprocessor pipeline for data operations while said second DMA controller ( 122 D) and said second cache controller and cache bank module ( 122 D) utilize said second internal cache ( 110 D) and second external cache and memory module ( 105 D) for memory storage;

said third DMA controller ( 122 R) and said third cache controller and cache bank module ( 126 R) communicate with said microprocessor pipeline for register operations while said third DMA controller ( 122 R) and said third cache controller and said cache bank module ( 126 R) utilize said third internal cache ( 110 R) and said third external cache and memory module ( 105 R) for memory storage;

said fourth DMA controller ( 132 ) and said fourth cache controller and cache bank module ( 136 ) communicate with said microprocessor pipeline for pipeline state operations while said fourth DMA controller ( 132 ) and said fourth cache controller and cache bank module ( 136 ) utilize said fourth internal cache ( 110 P) and fourth external cache and memory module ( 105 P) for memory storage.

2. A microprocessor architecture according to claim 1 wherein:

said first, second, third, and fourth cache controller and cache bank modules ( 126 I, 126 D, 126 R, 136 ) contain respective cache banks ( 250 I, 250 D, 250 R, 350 ) containing permission fields ( 610 . m ) for implementing OS information assurance features ( 650 ) in hardware, said permission fields ( 610 . m ) protecting each cache bank ( 250 I.B(m), 250 D.B(m), 250 R.B(m), 350 .B(m)), said cache banks containing a plurality of memory cells, wherein each memory cell contains permission fields ( 624 , 625 , 626 , 630 , 632 ) implementing information assurance, said permission fields providing protection against malware.

3. A microprocessor architecture according to claim 1 wherein:

said microprocessor architecture ( 100 ) allows the microprocessor pipeline ( 190 ) to run instructions, while said DMA controllers ( 122 I, 122 D, 122 R, 132 ) and said cache controller and cache bank modules ( 126 I, 126 D, 126 R, 136 ) handle overhead of a context switch, said microprocessor pipeline, said DMA controllers and said cache controller and cache bank modules all working in parallel.

4. A microprocessor architecture according to claim 2 , further comprising a permission bit IRegIO ( 650 E) providing for OS managed input/output control without any OS overhead for protecting said each cache bank and said memory cells from a malicious instruction and poorly coded software.

5. A microprocessor architecture according to claim 1 , wherein:

each of said cache bank controllers and cache banks incorporate a permission bit ( 650 D) providing OS level control over jump and branch on an index register instruction for preventing malware from utilizing the jump or branch on the index register to protect areas of memory.

6. A microprocessor architecture according to claim 1 , further comprising swapping set cache banks ( 250 I.B(swp), 250 D.B(swp), 250 R.B(swp) 350 .B(swp)) for operating a reduced voltage and clock frequency, and inactive cache banks ( 250 I.B(ina), 250 D.B(ina), 250 R.B(ina), 350 . B(ina)) located within said first, said second, said third and said fourth cache controller and cache bank modules ( 126 I, 126 D, 126 R, 136 ).

7. A microprocessor architecture according to claim 1 , further comprising:

a table ( 700 ) listing all possible library functions and providing access and permission control for software running on the microprocessor architecture.