Readout circuit and semiconductor device
Provided is a readout circuit capable of detecting inversion of retained data caused by a noise, such as static electricity. The readout circuit is configured to retain opposing data in a first latch circuit and a second latch circuit in a readout period so as to be capable of detecting an anomaly of the retained data by making use of the fact that the data in the first latch circuit and the second latch circuit are inverted in the same direction due to a noise, such as static electricity.
1. A readout circuit comprising:
a first switch that reads data at an input terminal;
a first latch circuit that retains the data read by the first switch;
a second switch that initializes data in the first latch circuit; and
an output terminal connected to the first latch circuit that outputs the data in the first latch circuit,
wherein the readout circuit further comprises:
a second latch circuit that retains data obtained by inverting the data in the first latch circuit; and
a detection circuit having a first input connected to the first latch circuit and a second input connected to the second latch circuit, that detects a data anomaly, in which either the data in the first latch circuit or the data in the second latch circuit is inverted, and
the detection circuit having an output connected to a detection terminal and outputs a detection signal from the detection terminal upon detection of a data anomaly.
2. The readout circuit according to claim 1 , comprising:
a third switch that initializes the second latch circuit to data obtained by inverting initial data in the first latch circuit; and
a fourth switch that inverts the data in the second latch circuit in the case where the data retained in the first latch circuit and initial data in the second latch circuit are the same.
3. The readout circuit according to claim 1 , wherein the first latch circuit and the second latch circuit share the same power supply line and are adjacently disposed.
4. The readout circuit according to claim 2 , wherein the first latch circuit and the second latch circuit share the same power supply line and are adjacently disposed.
5. A semiconductor device comprising:
a memory element connected to the input terminal; and
the readout circuit according to claim 1 that retains data read from the memory element and detects an anomaly of the retained data.
6. The readout circuit according to claim 1 , wherein the detection circuit comprises an XNOR circuit.