Switched capacitance converter

1. A system, comprising:

a first capacitor group to facilitate determination of a first bit;

a second capacitor group to, in combination with the first capacitor group, facilitate determination of a second bit; and

a delayed clock switch to engage the second capacitor group after determination of the first bit.

2. The system of claim 1 , where the first bit comprises a most significant bit.

3. The system of claim 1 , where the second bit comprises a least significant bit.

4. The system of claim 1 , where the first capacitor group comprises a first capacitor paired with a second capacitor in the second capacitor group.

5. The system of claim 4 , where the first capacitor has less capacitance than the second capacitor.

6. The system of claim 4 , where the first capacitor is situated in parallel with the second capacitor.

7. The system of claim 4 , further comprising a latch to drive the first and second capacitors.

8. The system of claim 4 , where the first capacitor comprises a set of unitary capacitors situated in parallel.

9. The system of claim 4 where a first ratio of the capacitance of the first capacitor to the capacitance of the first capacitor group is similar to a second ratio of the capacitance of the first and second capacitors to the capacitance of the first and second capacitor groups.

10. The system of claim 4 , further comprising a split-capacitance analog-to-digital converter; and

where the first capacitor group further comprises a third capacitor with a capacitance equal to a capacitance of the first capacitor;

where the first capacitor is configured to initialize in a logical high state; and

where the third capacitor is configured to initialize in a logical low state.

11. The system of claim 1 comprising an analog-to-digital converter with sampling cycle and an associated sampling frequency, and the delayed clock switch is configured to operate at the sampling frequency.

12. The system of claim 1 , further comprising a second delayed clock switch to disengage the second capacitor group from a ground.

13. A method, comprising:

determining a first number of bits based on a first capacitor group;

receiving a delayed clock signal;

engaging a second capacitor group based on the delayed clock signal; and

determining a second number of bits based on the first and second capacitor groups.

14. The method of claim 13 , further comprising engaging a latch to drive a first capacitor of the first group and a second capacitor of the second group.

15. The method of claim 14 , further comprising:

operating the first capacitor in a engaged state prior to reception of the delayed clock signal; and

operating the second capacitor in a disengaged state prior to reception of the delayed clock signal.

16. The method of claim 15 , further comprising, prior to reception of the delayed clock signal, determining a most significant bit based on the engaged state of the first capacitor and the disengaged state of the second capacitor.

17. The method of claim 13 , further comprising:

sampling a positive signal via the first capacitor group;

sampling a negative signal via a third capacitor group;

generating a positive output based on the first capacitor group;

generating a negative output based on the third capacitor group;

comparing the positive and negative outputs;

based on the comparison, switching a capacitor within the first group or third group to a logical low; and

based on the switching, determining a bit assignment.

18. A device, comprising;

a first latch associated with a most significant bit (MSB);

a second latch associated with a least significant bit (LSB);

a delayed clock configured to generate a delayed clock signal after a determination of the MSB and prior to a determination of the LSB;

a first capacitor configured to be engaged prior to generation of the delayed clock signal, the first capacitor configured to be driven by the first latch;

a second capacitor configured to be disengaged prior to generation of the delayed clock signal, the second capacitor configured to be driven by the second latch;

a third capacitor configured to be disengaged prior to generation of the delayed clock signal the third capacitor configured to be driven by the first latch; and

a controller configured to engage the second and third capacitors in response to the generation of the delayed clock signal.

19. The device of claim 18 , where the determination of the MSB configured to be based on a switching state of the first and third capacitors.

20. The device of claim 18 , where a first ratio of a capacitance of the first capacitor to a fractional capacitance corresponds to a weight; and

where a second ratio of the capacitance of the first capacitor and a capacitance of the third capacitor to a total capacitance corresponds to the weight.