IP Library Granted Patent US 9,070,627
Granted Patent B2
US 9,070,627 · App. 14/031,000 · Granted Jun 30, 2015

Interposer package-on-package structure

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Quick Facts
Patent No.
US 9,070,627
App. No.
14/031,000
Granted
Jun 30, 2015
Kind
B2
Abstract

An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

Claims (35)

1. An integrated circuit (IC) package comprising:

an IC die having a first surface and a second surface opposite of the first surface, wherein the second surface of the IC die includes a first plurality of electrical contact members;

a bottom substrate having a first surface and a second surface, the second surface of the bottom substrate being opposite of the first surface of the bottom substrate, wherein the first surface of the bottom substrate is coupled to the IC die via the first plurality of electrical contact members, wherein the second surface of the bottom substrate includes a second plurality of electrical contact members; and

an interposer substrate coupled to the first surface of the IC die via an adhesive material, wherein the adhesive material is disposed at a plurality of locations on a surface of the interposer substrate and the first surface of the IC die, wherein the interposer substrate includes a third plurality of electrical contact members, wherein the interposer substrate is coupled to the first surface of the bottom substrate via the third plurality of electrical contact members.

2. The IC package of claim 1 , wherein the IC die is a flip chip die.

3. The IC package of claim 1 , further comprising a non-conductive adhesive disposed on one or more portions of the first surface of the bottom substrate at a periphery of the bottom substrate, wherein the surface of the interposer substrate makes contact with the non-conductive adhesive, and wherein the non-conductive adhesive at least partially encapsulates the second plurality of electrical contact members.

4. The IC package of claim 1 , further comprising a mold compound disposed on the first surface of the bottom substrate, wherein the second plurality of electrical contact members extend above a surface of the mold compound.

5. The IC package of claim 4 , wherein the interposer substrate is coupled to the surface of the mold compound via the adhesive material, wherein the adhesive material is disposed where an air gap is present between the surface of the mold compound and the surface of the interposer substrate, and wherein the mold compound encapsulates the IC die.

6. The IC package of claim 4 , wherein the mold compound partially encapsulates the IC die, and wherein the adhesive material is disposed where an air gap is present between the surface of the mold compound and the surface of the interposer substrate.

7. The IC package of claim 6 , wherein the interposer substrate is coupled to the first surface of the IC die via the adhesive material.

8. The IC package of claim 6 , wherein the interposer substrate is coupled to the surface of the mold compound and the first surface of the IC die via the adhesive material.

9. The IC package of claim 4 , wherein the adhesive material is disposed at corner locations on the surface of the mold compound.

10. The IC package of claim 1 , wherein the adhesive material has a pattern that includes a plurality of intersecting cross-shaped structures, and wherein the adhesive material is disposed at a center location of the first surface of the IC die or corresponding location on the interposer substrate.

11. The IC package of claim 1 , wherein the adhesive material has a pattern that includes a plurality of linear-shaped structure in a circular arrangement, and wherein the adhesive material is disposed at a center location of the first surface of the IC die or corresponding location on the interposer substrate.

12. The IC package of claim 1 , wherein the adhesive material has a pattern that includes a plurality of circular-shape structures, and wherein the adhesive material is disposed at corner locations of the first surface of IC die or corresponding location on the interposer substrate with one circular-shaped structure at a respective corner location.

13. The IC package of claim 1 , wherein the adhesive material has a pattern that includes a circular-shaped structure, and wherein the adhesive material is disposed at a center location of the first surface of IC die or corresponding location on the interposer substrate.

14. The IC package of claim 1 , wherein the adhesive material is disposed at corner locations on the first surface of the IC die.

15. The IC package of claim 1 , wherein the adhesive material is disposed on a portion of the first surface of the IC die.

16. A method of manufacturing an integrated circuit (IC) package, the method comprising:

coupling a first plurality of electrical contact members to a surface of an interposer substrate;

mounting a first surface of an IC die to a first surface of a bottom substrate, wherein the IC die includes a second plurality of electrical contact members;

disposing an underfill compound between the first surface of the IC die and the first surface of the bottom substrate, wherein the underfill compound is embedded within the second plurality of electrical contact members;

disposing an adhesive material at a plurality of locations on a second surface of the IC die;

coupling the surface of the interposer substrate to the first surface of the bottom substrate, wherein the second surface of the IC die is bonded to at least a portion of the surface of the interposer substrate via the adhesive material; and

coupling a third plurality of electrical contact members to a second surface of the bottom substrate opposite of the first surface of the bottom substrate.

17. The method of claim 16 , wherein coupling the surface of the interposer substrate to the first surface of the bottom substrate comprises applying a reflow process with a reflow temperature to at least cure the adhesive material.

18. The method of claim 17 , further comprising coupling a fourth plurality of electrical contact members to the first surface of the bottom substrate.

19. The method of claim 18 , further comprising disposing a mold compound to the first surface of the bottom substrate, wherein the mold compound encapsulates the fourth plurality of electrical contact members.

20. The method of claim 19 , further comprising applying a laser ablation process to the mold compound, wherein portions at a surface of the mold compound directly above the fourth plurality of electrical contact members are removed by the laser ablation process, and wherein the adhesive material is disposed on at least a portion of the surface of the mold compound.

21. The method of claim 20 , wherein coupling the surface of the interposer substrate to the first surface of the bottom substrate comprises coupling the first plurality of electrical contact members to the fourth plurality of electrical contact members, wherein the first plurality of electrical contact members are aligned with the fourth plurality of electrical contact members, and wherein the portion of the surface of the mold compound disposed with the adhesive material is bonded to the surface of the interposer substrate.

22. An integrated circuit (IC) package comprising:

an IC die having a first surface and a second surface opposite of the first surface, wherein the second surface of the IC die includes a first plurality of electrical contact members;

a bottom substrate having a first surface and a second surface, the second surface of the bottom substrate being opposite of the first surface of the bottom substrate, wherein the first surface of the bottom substrate is coupled to the IC die via the first plurality of electrical contact members, wherein the second surface of the bottom substrate includes a second plurality of electrical contact members;

a mold compound disposed on the first surface of the bottom substrate, wherein a third plurality of electrical contact members extend above a top surface of the mold compound; and

an interposer substrate coupled to the top surface of the mold compound via an adhesive material, wherein the adhesive material is disposed at a plurality of locations on a surface of the interposer substrate and the top surface of the mold compound, wherein the interposer substrate includes the third plurality of electrical contact members, wherein the interposer substrate is coupled to the first surface of the bottom substrate via the third plurality of electrical contact members.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2013
From: ZHAO, SAM ZIQUN; KHAN, REZAUR RAHMAN
To: BROADCOM CORPORATION
Reel/Frame 031254/0119 →