Method and apparatus for a SuperSpeed USB bus powered real-time spectrum analyzer
View Patent ↗An RF processing module that when coupled to a computer having appropriate signal processing software will function as a spectrum analyzer. The RF processing module has a first stage mixer and a switch that allows either port of the first stage mixer to be selected as the input and receive the RF signal. The RF processing module has a sample packing buffer that packs digitized signal samples into a fewer number of longer words and loads the words into a circular buffer and from then to one of two DMA channels on a USB link. The circular buffer can be emptied faster than it can be filled, allowing the sample packing buffer to create time intervals for a USB controller to switch DMA channels. LO leakage through the mixer-to-IF path is used to self-calibrate the filter's frequency response as temperature and other environmental factors change.
1. A device comprising:
a clock configured for generating a clock signal comprising a sequence of cycles;
a sample packing buffer configured for receiving a stream of digital signal samples, no more than one digital signal sample per cycle of the clock signal, and configured for packing the digital signal samples into a stream of words, wherein each word consists of one of the digital signal samples and a portion of another of the digital signal samples;
a Universal Serial Bus (USB) controller configured for receiving the stream of words from the sample packing buffer, no more than one of the stream of words per cycle of the clock signal, including a first set of words, a second set of words and a third set of words; and
wherein the USB controller is configured for transmitting the first set of words from a first Direct Memory Access (DMA) buffer over a first DMA channel while receiving the second set of words into a second DMA buffer, then switching to transmitting the second set of words from the second DMA buffer over a second DMA channel while receiving the third set of words into the first DMA buffer.
2. The device of claim 1 ,
wherein the first DMA channel has a first USB endpoint; and
wherein the second DMA channel has a second USB endpoint.
3. The device of claim 1 ,
wherein the digital signal samples are each n bits in length, the words are each (m+n) bits in length; and
wherein the sample packing buffer is configured for packing, for c cycles of the clock signal, m bits of a first of c digital signal samples along with one of the other c digital signals in each of (c−1) words, where c=((m+n)/m) and n evenly divides by m, where n and m are integers greater than 1.
4. The device of claim 3 ,
wherein the sample packing buffer has a circular buffer;
wherein the sample packing buffer is configured for loading one word into the circular buffer for each of (c−1) out of the c cycles of the clock signal, but not loading any word in one of the c cycles of the clock signal; and
wherein the sample packing buffer is configured to be capable of unloading one word from the circular buffer for each of the c cycles of the clock signal.
5. The device of claim 2 ,
wherein n=14 and m=2.
6. The device of claim 1 ,
a mixer configured for converting an Radio Frequency (RF) signal to an intermediate Frequency (IF) signal; and
an IF-to-bits module configured for providing the stream of digital signal samples by converting the IF signal.
7. The device of claim 6 ,
wherein the USB controller is a USB 3.0 SuperSpeed peripheral controller configured for transmitting 32 kB packets of 16,384 words packed with 18,688 14-bit digital signal samples.
8. The device of claim 7 ,
wherein said packets contain additional information for triggering and data integrity to enable applications such as Global Positioning System (GPS) time stamping and time gated spectrum analysis.
9. The device of claim 6 ,
wherein the IF-to-bits module has a Surface Acoustic Wave (SAW) filter that is self-calibrated using local oscillator leakage from the mixer.
10. A method, comprising the steps of:
receiving a clock signal comprising a sequence of cycles of the clock signal;
receiving a stream of digital signal samples, no more than one digital signal sample per cycle of the clock signal;
packing the digital signal samples into a stream of words, wherein each word consists of one of the digital signal samples and a portion of another of the digital signal samples;
loading the stream of words into a circular buffer, no more than one of the stream of words per cycle of the clock signal;
unloading the stream of words from the circular buffer, no more than one of the stream of words per cycle of the clock signal, the stream of words including a first set of words, a second set of words and a third set of words; and
transmitting the first set of words from a first Direct Memory Access (DMA) buffer over a first DMA channel of a Universal Serial Bus (USB) link while receiving the second set of words into a second DMA buffer, then switching to transmitting the second set of words from the second DMA buffer over a second DMA channel of the USB link while receiving the third set of words into the first DMA buffer.
11. The method of claim 10 ,
wherein the digital signal samples are each n bits in length, the words are each (m+n) bits in length; and
wherein packing the digital signal samples into the stream of words further comprises packing, for c cycles of the clock signal, m bits of a first of c digital signal samples along with one of the other c digital signals in each of (c−1) words, where c=((m+n)/m) and n evenly divides by m, where n and m are integers greater than 1.
12. The method of claim 11 ,
wherein loading the stream of words into the circular buffer further comprises loading one of the stream of words into the circular buffer for each of (c−1) out of the c cycles of the clock signal, but not loading any one of the stream of words into the circular buffer during one of the c cycles of the clock signal; and
wherein unloading the stream of words from the circular buffer further comprises unloading one of the stream of words from the circular buffer for each of the c cycles of the clock signal.
13. The method of claim 12 ,
wherein n=14 and m=2.