IP Library Granted Patent US 9,023,674
Granted Patent B2
US 9,023,674 · App. 14/033,089 · Granted May 5, 2015

Biosensing well array with protective layer

Inventors: Wei-Cheng Shen (Tainan, TW); Yi-Hsien Chang (Shetou Township, TW); Shih-Wei Lin (Taipei, TW); Chun-Ren Cheng (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
G01N27/4148G01N27/4145
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Quick Facts
Patent No.
US 9,023,674
App. No.
14/033,089
Granted
May 5, 2015
Kind
B2
Abstract

The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET includes a microwells having a sensing layer, a top metal stack under the sensing layer, and a multi-layer interconnect (MLI) under the top metal stack. The top metal stack includes a top metal and a protective layer over and peripherally surrounding the top metal.

Claims (68)

1. A method of making a BioFET device, comprising:

forming a plurality of FETs on a semiconductor substrate, wherein the plurality of FETs each includes a gate structure formed on a first surface of the semiconductor substrate and a channel region;

forming a gate contact on the gate structure in each of the plurality of FETs;

forming one or more metal interconnect layers over the plurality of FETs;

forming a plurality of top metal stacks having a protective layer on sidewalls of the top metal stacks;

forming a passivation layer over the plurality of top metal stacks;

etching microwells in the passivation layer to expose a subset of the plurality of top metal stacks, wherein a bottom surface area of the microwells is larger than respective top surfaces of respective ones of the subset of the plurality of top metal stacks;

depositing a sensing layer in the microwells and over a field portion between the microwells, wherein the sensing layer fills any openings between the subset of the plurality of top metal stacks and the passivation layer; and

removing at least the field portion of the sensing layer.

2. The method of claim 1 , further comprising:

forming respective openings over respective ones of a second subset of the plurality of top metal stacks;

removing a protective layer and an antireflective layer in the second subset of the plurality of top metal stacks; and

forming respective contacts between the top metal in the second subset of the plurality of top metal stacks and respective package terminals.

3. The method of claim 1 , wherein the forming a plurality of top metal stacks comprises:

depositing an underlayer on a planarized semiconductor substrate surface;

depositing a top metal on the underlayer;

depositing an antireflective layer on the top metal;

depositing and patterning a first photoresist layer over the antireflective layer;

etching a first pattern through the underlayer to form separate stacks of the underlayer, top metal, and antireflective layer;

depositing a protective layer covering sidewalls of the top metal; and

separating the protective layer according to the pattern;

wherein each top metal stacks is a stack comprising the underlayer, the top metal, the antireflective layer, and a protective layer over the antireflective layer and peripherally surrounding the top metal.

4. The method of claim 3 , wherein separating the protective layer comprises

anisotropically plasma etching the protective layer to remove a bottom portion of the protective layer, said bottom portion disposed between the top metal stacks.

5. The method of claim 3 , wherein separating the protective layer comprises

depositing a second photoresist layer;

patterning the second photoresist layer to expose a portion of the protective layer between the top metal stacks;

removing the exposed portions of the protective layer; and

removing the second photoresist.

6. The method of claim 5 , wherein the patterning the second photoresist layer comprises exposing the second photoresist to light generated from a photomask used to pattern the first photoresist layer at an intensity level different from an intensity level to pattern the first photoresist layer.

7. The method of claim 3 , wherein the depositing a protective layer comprises sputtering a titanium nitride target.

8. The method of claim 3 , wherein the depositing a protective layer comprises depositing a titanium nitride using atomic layer deposition.

9. The method of claim 1 , wherein the depositing a sensing layer comprises depositing a high-k dielectric layer.

10. The method of claim 1 , wherein the protective layer is titanium nitride.

11. A method of making a BioFET device, comprising:

forming on a planar surface of a substrate a top metal layer;

patterning the top metal layer to form a top metal stack having a top surface and a sidewall;

forming a protective layer having a protective layer top portion extending along the top surface of the top metal stack and having a protective layer sidewall portion extending along the sidewall of the top metal stack;

depositing a passivation layer on the protective layer;

patterning the passivation layer to form an opening, wherein the opening has a bottom formed by the protective layer top portion and the opening has a passivation layer sidewall; and

forming a sensing layer on the protective layer top portion and the protective layer sidewall portion and on the passivation layer sidewall.

12. The method of claim 11 , wherein the step of forming on a planar surface of a substrate a top metal layer comprises:

depositing on the planar surface a conductive underlayer; and

depositing on the conductive underlayer a conductive layer.

13. The method of claim 11 , wherein the step of forming a protective layer comprises:

blanket depositing the protective layer; and

patterning the protective layer using a dry etching process.

14. The method of claim 13 , further comprising patterning the protective layer using a first photomask pattern and further comprising patterning the top metal layer using the first photomask pattern.

15. The method of claim 11 , wherein the step of forming a sensing layer on the protective layer top portion and the protective layer sidewall portion and on the passivation layer sidewall comprises:

blanket depositing the protective layer on the protective layer top portion, the protective layer sidewall portion, the passivation sidewall, and atop the passivation layer; and

removing the sensing layer from atop the passivation layer.

16. A method of making a BioFET device, comprising:

forming a transistor on a semiconductor substrate;

forming at least one intermediate metallization layer above and electrically contacting the transistor;

forming a top metal stack above and electrically contacting the at least one intermediate metallization layer, wherein the top metal stack includes a conductive feature having a top surface and sidewalls;

forming over the top surface and sidewalls a patterned protective layer; and

forming on the patterned protective layer a sensing layer, wherein the sensing layer extends along the top surface and along the sidewalls.

17. The method of claim 16 , wherein the step of forming top metal stack includes:

blanket depositing an underlayer, a conductive layer, and an antireflective layer, and patterning the underlayer, the conductive layer, and the antireflective layer using a photomask pattern.

18. The method of claim 17 , further comprising forming a microwell above the top metal stack by:

depositing a passivation layer on the top metal stack; and

patterning the passivation layer to expose a top surface of the patterned protective layer.

19. The method of claim 17 , wherein the step of forming over the top surface and sidewalls a patterned protective layer includes:

blanket depositing a protective layer; and

patterning the protective layer using the photomask pattern.

20. The method of claim 16 , further comprising:

forming a second top metal stack above and electrically contacting the at least one intermediate metallization layer, wherein the top metal stack includes a conductive feature having a top surface and sidewalls;

removing the patterned protective layer from the top surface of the second top metal stack; and electrically connecting the second top metal stack to a package terminal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2017
From: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
To: LIFE TECHNOLOGIES CORPORATION
Reel/Frame 040876/0228 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2013
From: SHEN, WEI-CHENG; CHANG, YI-HSIEN; LIN, SHIH-WEI; CHENG, CHUN-REN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 031252/0791 →
Continuity (1)
Related Publication 20150084099A1 · Mar 26, 2015