Network interface controller with direct connection to host memory

1. A network interface device for a host computer, the device comprising:

a network interface, configured to transmit and receive data packets to and from a network;

packet processing logic, configured to transfer data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer; and

a memory controller, comprising:

a first memory interface configured to be connected to the system memory;

a second memory interface, configured to be connected to a host complex of the host computer; and

switching logic, which alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration,

wherein the switching logic is configured, in the pass-through configuration, as a transparent channel, whereby the host complex accesses addresses in the system memory as though the system memory was connected directly to the host complex.

2. The device according to claim 1 , wherein the system memory includes dynamic random access memory (DRAM), and wherein the first and second memory interface are Double Data Rate (DDR) interfaces.

3. The device according to claim 1 , and comprising a host interface, which is configured to exchange traffic with the host complex via an expansion bus of the host computer, which is separate from the second memory interface.

4. The device according to claim 3 , wherein the expansion bus comprises a peripheral component interconnect (PCI) bus.

5. The device according to claim 3 , wherein the traffic exchanged with the host complex via the expansion bus comprises instructions to the packet processing logic with respect to the data packets that are transmitted to and received from the network.

6. A network interface device for a host computer, the device comprising:

a network interface, configured to transmit and receive data packets to and from a network;

packet processing logic, configured to transfer data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer;

a memory controller, comprising:

a first memory interface configured to be connected to the system memory;

a second memory interface, configured to be connected to a host complex of the host computer; and

switching logic, which alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration; and

a host interface, which is configured to exchange traffic with the host complex via an expansion bus of the host computer, which is separate from the second memory interface,

wherein the traffic exchanged with the host complex via the expansion bus comprises transactions on the expansion bus that are initiated by the memory controller in order to maintain cache coherency between the host complex and the system memory.

7. The device according to claim 6 , wherein the switching logic is configured, in the pass-through configuration, as a transparent channel, whereby the host complex accesses addresses in the system memory as though the system memory was connected directly to the host complex.

8. A computer system, comprising:

a system memory;

a host complex; and

a network interface controller (NIC), which comprises:

a network interface, configured to transmit and receive data packets to and from a network;

packet processing logic, configured to transfer data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to the system memory; and

a memory controller, comprising:

a first memory interface connected to the system memory;

a second memory interface connected to a host complex; and

switching logic, which alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration,

wherein the switching logic is configured, in the pass-through configuration, as a transparent channel, whereby the host complex accesses addresses in the system memory as though the system memory was connected directly to the host complex.

9. The system according to claim 8 , wherein the system memory comprises dynamic random access memory (DRAM), and wherein the first and second memory interface are Double Data Rate (DDR) interfaces.

10. The system according to claim 8 , and comprising an expansion bus linked to the host complex, wherein the NIC comprises a host interface, which is coupled to exchange traffic with the host complex via the expansion bus and which is separate from the second memory interface.

11. The system according to claim 10 , wherein the expansion bus comprises a peripheral component interconnect (PCI) bus.

12. The system according to claim 10 , wherein the traffic exchanged with the host complex via the expansion bus comprises instructions to the packet processing logic with respect to the data packets that are transmitted to and received from the network.

13. A computer system, comprising:

a system memory;

a host complex;

an expansion bus linked to the host complex; and

a network interface controller (NIC), which comprises:

a network interface, configured to transmit and receive data packets to and from a network;

packet processing logic, configured to transfer data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to the system memory;

a memory controller, comprising:

a first memory interface connected to the system memory;

a second memory interface connected to a host complex; and

switching logic, which alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration; and

a host interface, which is coupled to exchange traffic with the host complex via the expansion bus and which is separate from the second memory interface,

wherein the traffic exchanged with the host complex via the expansion bus comprises transactions on the expansion bus that are initiated by the memory controller in order to maintain cache coherency between the host complex and the system memory.

14. The system according to claim 13 , wherein the switching logic is configured, in the pass-through configuration, as a transparent channel, whereby the host complex accesses addresses in the system memory as though the system memory was connected directly to the host complex.

15. A method for data communications, comprising:

connecting a first memory interface of a network interface controller (NIC) to a system memory of a host computer;

connecting a second memory interface of the NIC to a host complex of the host computer;

transmitting and receiving data packets to and from a network via a network interface of the NIC while transferring data, via packet processing logic in the NIC, to and from the data packets by direct memory access (DMA) between the packet processing logic and the system memory; and

alternately coupling the first memory interface to the packet processing logic in a DMA configuration to enable transfer of the data between the packet processing logic and the system memory, and to the second memory interface in a pass-through configuration to enable direct data transfer between the host complex and the system memory,

wherein coupling the first memory interface to the second memory interface in the pass-through configuration comprises providing a transparent channel, over which the host complex accesses addresses in the system memory as though the system memory was connected directly to the host complex.

16. The method according to claim 15 , wherein the system memory includes dynamic random access memory (DRAM), and wherein the first and second memory interface are Double Data Rate (DDR) interfaces.

17. The method according to claim 15 , and comprising connecting a host interface of the NIC to exchange traffic with the host complex via an expansion bus of the host computer, which is separate from the second memory interface.

18. The method according to claim 17 , wherein the expansion bus comprises a peripheral component interconnect (PCI) bus.

19. The method according to claim 17 , wherein connecting the host interface comprises receiving, via the expansion bus, instructions sent from the host complex to the packet processing logic with respect to the data packets that are transmitted to and received from the network.

20. A method for data communications, comprising:

connecting a first memory interface of a network interface controller (NIC) to a system memory of a host computer;

connecting a second memory interface of the NIC to a host complex of the host computer;

transmitting and receiving data packets to and from a network via a network interface of the NIC while transferring data, via packet processing logic in the NIC, to and from the data packets by direct memory access (DMA) between the packet processing logic and the system memory;

alternately coupling the first memory interface to the packet processing logic in a DMA configuration to enable transfer of the data between the packet processing logic and the system memory, and to the second memory interface in a pass-through configuration to enable direct data transfer between the host complex and the system memory; and

connecting a host interface of the NIC to exchange traffic with the host complex via an expansion bus of the host computer, which is separate from the second memory interface,

wherein connecting the host interface comprises initiating transactions on the expansion bus between the memory controller and the host complex in order to maintain cache coherency between the host complex and the system memory.

21. The method according to claim 20 , wherein coupling the first memory interface to the second memory interface in the pass-through configuration comprises providing a transparent channel, over which the host complex accesses addresses in the system memory as though the system memory was connected directly to the host complex.