Semiconductor memory circuit
View Patent ↗Provided is a semiconductor memory circuit excellent in long-term reliability and reading characteristics and having low current consumption. The semiconductor memory circuit includes: a first inverter; a first non-volatile memory, which is electrically writable; a second inverter; and a second non-volatile memory, the first inverter having an output connected to a source of the first non-volatile memory, the first non-volatile memory having a drain connected to an input of the second inverter, the second inverter having an output connected to a source of the second non-volatile memory, the second non-volatile memory having a drain connected to an input of the first inverter, the drain of the second non-volatile memory serving as an output of the semiconductor memory circuit.
1. A semiconductor memory circuit, comprising:
a first inverter;
a first non-volatile memory, which is electrically writable;
a second inverter; and
a second non-volatile memory,
the first inverter having an output connected to a source of the first non-volatile memory,
the first non-volatile memory having a drain connected to an input of the second inverter,
the second inverter having an output connected to a source of the second non-volatile memory,
the second non-volatile memory having a drain connected to an input of the first inverter,
the drain of the second non-volatile memory serving as an output of the semiconductor memory circuit.
2. A semiconductor memory circuit according to claim 1 , wherein the first non-volatile memory and the second non-volatile memory each include a control gate having a potential fixed to one of a VDD level and a VSS level.
3. A semiconductor memory circuit according to claim 1 :
wherein the first non-volatile memory includes a control gate connected to the source of the first non-volatile memory; and
wherein the second non-volatile memory includes a control gate connected to the source of the second non-volatile memory.
4. A semiconductor memory circuit according to claim 1 , further comprising:
a circuit for controlling an operation of each transistor included in the first inverter, and a circuit for controlling an operation of each transistor included in the second inverter;
a transistor, which is arranged between wiring for connecting an output of the first non-volatile memory and a downstream one of the first inverter and the second inverter, and one of VSS and VDD, and a transistor, which is arranged between wiring for connecting an output of the second non-volatile memory and a downstream one of the first inverter and the second inverter, and one of VSS and VDD,
wherein the drain of each of the first non-volatile memory and the second non-volatile memory is connectable to the one of VSS and VDD via the transistor.
5. A semiconductor memory circuit according to claim 1 , further comprising a capacitor arranged between the input of at least one of the first inverter and the second inverter, and one of VSS and VDD.
6. A semiconductor memory circuit according to claim 1 , further comprising a PN junction in a reverse direction, which is arranged between the input of at least one of the first inverter and the second inverter, and one of VSS and VDD.
7. A semiconductor memory circuit according to claim 1 , further comprising a resistor arranged in series to at least one of wiring on the source side and wiring on the drain side of each of the first non-volatile memory and the second non-volatile memory.