Memory storage device and method of manufacturing the same
View Patent ↗A memory storage device including: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.
1. A method of manufacturing a memory storage device, the method comprising:
(a) forming, in an insulating layer, a connection hole extending from a surface thereof to a connection point in a lower layer;
(b) forming, in the connection hole, a metal film with thickness smaller than a depth of the connection hole;
(c) filling a remainder of the connection hole and covering the insulating layer surface with a metal nitride layer;
(d) removing those portions of the metal film and the metal nitride layer present above the insulating layer surface;
(e) nitriding a portion of the metal film at the insulating layer surface and insulate un-nitrided metal film from the insulating surface; and
(f) forming a the memory storage layer on the surface; and
(g) forming an upper electrode on the memory storage layer.
2. The method of claim 1 , wherein the nitriding of the metal film comprises performing a nitride plasma treatment.
3. The method of claim 1 , wherein the nitriding of the metal film comprises performing a heat treatment.
4. The method of claim 1 , wherein the metal film comprises Ti, Co, Ni, W, Ta or any combination of them.
5. A method of manufacturing a memory storage device, the method comprising:
(a) forming, in an insulating layer, a connection hole extending from a surface thereof to a connection point in a silicon layer, which is a lower layer;
(b) forming, in the connection hole, a metal film having a thickness smaller than a depth of the connection hole;
(c) forming a silicide layer from a reaction of the silicon layer and a portion of the metal film in contact with the silicon layer;
(d) removing that portion of the metal film not reacted with the silicon layer;
(e) filling a remainder of the connection hole and covering the surface with a metal nitride layer;
(f) removing that portion of the metal nitride layer above the surface of the insulating layer;
(g) forming a the memory storage layer on the insulating layer surface and the metal nitride layer; and
(h) forming an upper electrode on the memory storage layer.
6. The method claim 5 , wherein the metal film comprises Ti, Co, Ni, W, Ta or any combination of them.
7. A method of manufacturing a memory storage device, the method comprising:
(a) forming, in an insulating layer, a plug layer formed of polysilicon with a portion of the plug layer exposed at a surface of the insulating layer;
(b) forming a metal film on a surface extending across the insulating layer and the plug layer;
(c) forming a metal silicide layer due to a reaction of the plug layer and the metal layer in a portion of the metal layer in contact with the plug layer;
(d) removing that portion of the metal film not reacted with the plug layer;
(e) forming a the memory storage layer on the insulating layer surface and the metal silicide layer; and
(f) forming an upper electrode on the memory storage layer.
8. The method of claim 7 , wherein the metal film comprises Ti, Co, Ni, W, or Ta, or any combination of them.
9. The method of claim 1 , wherein:
each of steps (a) to (e) is performed simultaneously for a plurality of memory cells; and
each of the memory storage layer and the upper electrode layer are formed in common across all of the memory cells.
10. The method of claim 5 , wherein:
each of steps (a) to (f) is performed simultaneously for a plurality of memory cells; and
each of the memory storage layer and the upper electrode layer are formed in common across all of the memory cells.
11. The method of claim 7 , wherein:
each of steps (a) to (d) is performed simultaneously for a plurality of memory cells; and
each of the memory storage layer and the upper electrode layer are formed in common across all of the memory cells.