Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same

1. A method, comprising:

smoothing a surface of a dielectric buffer layer;

forming multiple layers of a thin film multi-level capacitor over the dielectric buffer layer, the forming of the multiple layers including providing high permittivity dielectric layers interleaved between electrode layers to form multiple capacitors stacked on each other, wherein pairs of the multiple capacitors share a common electrode therebetween, and wherein a bottom electrode of a bottom capacitor of the multiple capacitors is formed directly on the dielectric buffer layer;

annealing each capacitor layer before forming a successive capacitor layer;

forming a high density interconnect layer, wherein the dielectric buffer layer provides electrical isolation between the high density interconnect layer and the thin film multi-level capacitor; and

forming a contact via through the dielectric buffer layer and the high density interconnect layer to provide electrical contact for the thin film multi-level capacitor.

2. The method of claim 1 , wherein the smoothing of the surface is to a surface roughness (Ra) of less than or equal to 0.08 microns and substantially free of surface micropores.

3. The method of claim 1 , comprising performing a heat treatment after each electrode layer of the multi-level capacitor is formed, wherein the multiple capacitors are formed in a mesa structure.

4. The method of claim 1 , comprising performing a heat treatment after each electrode layer of the multi-level capacitor is formed, wherein a surface roughness (Ra) of the buffer layer after the smoothing is less than or equal to 0.06 micrometers (um) and wherein the multiple layers of the thin film multi-level capacitor are each single layers of a barium strontium titanium oxide dielectric material.

5. The method of claim 1 , wherein the multiple layers of the thin film multi-level capacitor are each single layers of a barium strontium titanium oxide dielectric material.

6. The method of claim 1 , further comprising:

depositing an interlayer dielectric layer over the dielectric buffer layer;

fabricating an additional passive thin film device on the interlayer dielectric layer; and

depositing an interconnect layer to electrically couple the additional passive thin film device to the thin-film multi-level capacitor.

7. The method of claim 1 , wherein the high permittivity dielectric layers comprise Barium Strontium Titanium Oxide forming a tunable capacitor, and wherein a first capacitor of the multiple capacitors has different capacitance-voltage characteristics than a second capacitor of the multiple capacitors.

8. The method of claim 1 , further comprising depositing the dielectric buffer layer on a ceramic substrate comprising one of AlN, Mg 2 SiO 4 or MgTiO 3 .

9. The method of claim 1 , wherein a first capacitor of the multiple capacitors is a voltage tunable capacitor, and wherein a second capacitor of the multiple capacitors is a fixed value capacitor.

10. The method of claim 9 , wherein the multiple capacitors are in a mesa structure.

11. The method of claim 1 , wherein the thin film multi-level capacitor has an overall capacitance density of about 10 fF/um 2 to about 390 fF/um 2 .

12. A method, comprising:

smoothing a surface of a glass dielectric buffer layer;

forming multiple layers of a thin film multi-level capacitor over the glass dielectric buffer layer, the forming of the multiple capacitor layers including providing high permittivity dielectric layers interleaved between electrode layers to form multiple capacitors stacked on each other, wherein pairs of the multiple capacitors share a common electrode therebetween, wherein at least one capacitor of the multiple capacitors is a voltage tunable capacitor;

annealing each capacitor layer before forming a successive capacitor layer; and

forming a high density interconnect layer, wherein the glass dielectric buffer layer provides electrical isolation between the high density interconnect layer and the thin film multi-level capacitor.

13. The method of claim 12 , wherein at least one second capacitor of the multiple capacitors is a fixed value capacitor.

14. The method of claim 12 , wherein at least one of the multiple layers of the thin film multi-level capacitor comprises a barium strontium titanium oxide dielectric material.

15. The method of claim 12 , comprising:

forming a contact via through the glass dielectric buffer layer and the high density interconnect layer to provide electrical contact between the thin film multi-level capacitor and a bonding pad formed on an underside of a substrate; and

performing a heat treatment after each electrode layer of the multi-level capacitor is formed, wherein the glass dielectric buffer layer surface is smoothed to a Ra roughness of less than or equal to 0.08 microns, wherein a bottom electrode of a bottom capacitor of the multiple capacitors is formed directly on the glass dielectric buffer layer, and wherein the multiple layers of the thin film multi-level capacitor are each single layers of a dielectric material.

16. A method, comprising:

smoothing a surface of a dielectric buffer layer;

forming multiple layers of a thin film multi-level capacitor over the dielectric buffer layer, the forming of the multiple layers including providing high permittivity dielectric layers directly interleaved between electrode layers to form multiple capacitors stacked on each other, wherein pairs of the multiple capacitors share a common electrode therebetween, wherein at least a first capacitor of the multiple capacitors is a tunable capacitor comprising barium strontium titanate; and

forming a high density interconnect layer, wherein the dielectric buffer layer provides electrical isolation between the high density interconnect layer and the thin-film multi-level capacitor.

17. The method of claim 16 , comprising:

forming a contact via through the dielectric buffer layer and the high density interconnect layer to provide electrical contact between the thin film multi-level capacitor and a bonding pad formed on an underside of a substrate; and

performing a heat treatment after each electrode layer of the multi-level capacitor is formed, wherein the dielectric buffer layer surface is smoothed to a Ra roughness of less than or equal to 0.08 microns.

18. The method of claim 16 , wherein a first capacitor of the multiple capacitors has different capacitance-voltage characteristics than a second capacitor of the multiple capacitors.

19. The method of claim 16 , comprising forming a protective coating on an underside of a substrate, wherein the multiple capacitors are formed in a mesa structure.