INTERCONNECT STRUCTURE AND FORMING METHOD THEREOF
An interconnect structure and a forming method thereof are provided. The method includes: providing a semiconductor substrate which has semiconductor devices formed therein; forming an interlayer dielectric layer on the semiconductor substrate; forming a conductive layer on the interlayer dielectric layer; forming a groove in the conductive layer and the interlayer dielectric layer, the groove having a depth smaller than a sum of a thickness of the conductive layer and a thickness of the interlayer dielectric layer and having a depth-to-width ratio greater than 0.8; and depositing an intermetallic dielectric layer to cover the conductive layer and fill the groove, and forming an air gap in the intermetallic dielectric layer in the groove. The depth-to-width ratio of the groove and a size of the air gap are increased. Therefore, parasitic capacitance between the adjacent interconnects is reduced, and the performance of the semiconductor devices is improved.
1 . A method for forming an interconnect structure, comprising:
providing a semiconductor substrate which has semiconductor devices formed therein;
forming an interlayer dielectric layer on the semiconductor substrate;
forming a conductive layer on the interlayer dielectric layer;
forming a groove in the conductive layer and the interlayer dielectric layer, the groove having a depth smaller than a sum of a thickness of the conductive layer and a thickness of the interlayer dielectric layer and having a depth-to-width ratio greater than 0.8; and
depositing an intermetallic dielectric layer to cover the conductive layer and fill the groove, and forming an air gap in the intermetallic dielectric layer in the groove.
2 . The method according to claim 1 , wherein the interlayer dielectric layer and the intermetallic dielectric layer comprise a low-K dielectric material or an ultra-low-K dielectric material.
3 . The method according to claim 1 , wherein the interlayer dielectric layer comprises silicon dioxide.
4 . The method according to claim 1 , wherein the intermetallic dielectric layer is formed by a plasma enhanced chemical vapor deposition process.
5 . The method according to claim 1 , wherein the intermetallic dielectric layer comprises silicon dioxide.
6 . The method according to claim 1 , wherein the conductive layer comprises aluminium or tungsten.
7 . The method according to claim 1 , wherein the groove is formed by a photoetching process or an etching process.
8 . An interconnect structure, comprising:
a semiconductor substrate which has semiconductor devices formed therein;
an interlayer dielectric layer formed on the semiconductor substrate;
interconnects formed on the interlayer dielectric layer;
grooves between the adjacent interconnects, the grooves having a depth smaller than a sum of a thickness of the interconnects and a thickness of the interlayer dielectric layer and having a depth-to-width ratio greater than 0.8; and
an intermetallic dielectric layer which covers the interconnects and fills the grooves which have air gaps formed therein.
9 . The interconnect structure according to claim 8 , wherein the interlayer dielectric layer and the intermetallic dielectric layer comprise a low-K dielectric material or an ultra-low-K dielectric material.
10 . The interconnect structure according to claim 8 , wherein the interlayer dielectric layer comprises silicon dioxide.
11 . The interconnect structure according to claim 8 , wherein the intermetallic dielectric layer comprises silicon dioxide.
12 . The interconnect structure according to claim 8 , wherein the interconnects comprise aluminium or tungsten.