Reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device

1. An electronic storage device-enabled method of reducing erase cycles in an electronic storage device that uses non-volatile solid-state memory devices, including erase-limited memory devices that each include a plurality of non-volatile memory cells, the method comprising:

creating a logical storage unit in one of the non-volatile memory cell, the logical storage unit comprising a first flop that includes at least one flop section, including a first flop section and a second flop section;

wherein the non-volatile solid-state memory devices are configured to reduce erase cycles;

mapping a first address to said first flop;

reading said flop sections from said first flop using a section selection sequence;

storing data associated with said first address in said first flop by writing said data into said first flop section and storing a first value representing said first flop section location into a valid flop section location;

if said data is changed, storing said changed data into said second flop section, assigning said first flop section with an invalid status, storing said changed data in said second flop section, and assigning a valid status to said changed data; and

limiting said data to have a data size that is no more than the flop section size of said at least one flop section.

2. The method of claim 1 , wherein said creating a first flop further includes:

erasing a first non-volatile memory cell associated with a first non-volatile solid-state memory device;

associating said first non-volatile memory cell to said first address; and

partitioning said first non-volatile memory cell into said first flop section and said second flop section.

3. The method of claim 1 , wherein said creating a first flop further includes:

erasing a first non-volatile memory cell and a second non-volatile memory cell that are associated with a first non-volatile solid state memory device;

associating said first and second cells to said first address; and

partitioning said first block into at least said first flop section and said second block into at least said second flop section.

4. The method of claim 1 , wherein said creating a first flop further includes erasing a first non-volatile memory cell that is associated with a first non-volatile solid-state memory device.

5. The method of claim 4 , wherein said first flop section includes a flop section size that is equal to the size of a minimum writable location defined for said first cell.

6. The method of claim 5 , wherein said minimum writable location is a partial page of said first cell.

7. The method of claim 5 , wherein said minimum writable location is a page of said first cell.

8. An apparatus comprising:

a storage device comprising a memory store that includes at least one non-volatile solid-state memory device, wherein the at least one non-volatile solid-state memory device is an erase-limited memory device;

wherein the at least one non-volatile solid-state memory device comprises at least one logical storage unit comprising a flop;

wherein the flop comprises a first flop section and second flop section;

wherein a first address is mapped to a first flop, a flop block is erased, and a plurality of flop sections are created from the first flop block; and

wherein write operations of data associated with the first address is limited to only a flop section that has not been previously used to store said data after initialization of said first flop.

9. The apparatus of claim 8 , .wherein said first flop block is re-initialized after all flop sections associated with the first flop block have been used in the write operations.

10. The apparatus of claim 8 , wherein the first flop section and the second flop section are included in a first cell from the non-volatile memory cells in a non-volatile solid-state memory device.

11. The apparatus of claim 8 , where the first flop section is a first cell from the non-volatile memory cells and the second flop section is in a second cell from the non-volatile memory cells in a non-volatile solid-state memory device.

12. The apparatus of claim 8 , where the first flop section is a first non-volatile memory cell in a first non-volatile solid-state memory device, and the second flop section is in a second non-volatile memory cell in a second non-volatile solid state memory device.

13. The apparatus of claim 8 , further comprising: a mapping structure for mapping a primary address to a set of at least one non-volatile memory cell, wherein the primary address is associated with data which is subject to the memory transaction request.

14. The apparatus of claim 13 , wherein the primary address comprises a logical block address and wherein the set of at least one non-volatile memory cell corresponds to a set of physical block addresses.

15. An electronic storage device-enabled method of initializing a logical storage unit for minimizing erase cycles in an electronic storage device, comprising:

selecting minimum erasable locations that will be used to initialize the logical storage unit, wherein the locations comprises non-volatile memory cells;

mapping a primary address to the minimum erasable locations;

erasing the minimum erasable locations in a logical storage unit in order to initialize a non-volatile memory cell;

calculating or obtaining initialization parameters, and storing the initialization parameters; and

initializing a section selection sequence, wherein a first minimum writeable location in an erased minimum erasable location in the section selection sequence is treated as an available flop section.

16. The method of claim 15 , wherein a size of one of the minimum erasable location is a page.

17. A computer program product comprising a non-transitory computer usable medium having control logic stored therein for causing a computer to facilitate in initializing a logical storage unit for minimizing erase cycles in an electronic storage device, said control logic comprising:

selecting minimum erasable locations that will be used to initialize the logical storage unit, wherein the locations comprises non-volatile memory cells;

mapping a primary address to the minimum erasable locations;

erasing the minimum erasable locations in a logical storage unit in order to initialize a non-volatile memory cell;

calculating or obtaining initialization parameters, and storing the initialization parameters; and

initializing a section selection sequence, wherein a first minimum writeable location in an erased minimum erasable location in the section selection sequence is treated as an available flop section.

18. The computer program product of claim 17 , wherein a size of one of the minimum erasable location is a page.

19. An electronic storage device-enabled method for reducing erase cycles in an electronic storage device, the method comprising:

initializing a first logical storage unit in a memory device by at least mapping a first address to the first logical storage unit, erasing a first logical storage unit block, and creating a plurality of logical storage unit sections from said first logical storage unit block; and

limiting memory device write operations of data associated with the first address to only a logical storage unit section that has not been previously used to store the data after initialization of the first logical storage unit.

20. The method of claim 19 , further comprising:

re-initializing said first logical storage unit block after all of said plurality of logical storage unit sections from said first logical storage unit block have been used in said write operations.

21. The method of claim 19 , further including:

using a mapping structure and a pointer to point said first address to a second address; and

using said pointer as said data.

22. The method of claim 19 , further comprising:

using a host address as said first address, and a local address as said second address.

23. A computer program product comprising a non-transitory computer usable medium having control logic stored therein for causing a computer to facilitate in reducing erase cycles in an electronic storage device, said control logic comprising:

initializing a first logical storage unit in a memory device by at least mapping a first address to the first logical storage unit, erasing a first logical storage unit block, and creating a plurality of logical storage unit sections from said first logical storage unit block; and

limiting memory device write operations of data associated with the first address to only a logical storage unit section that has not been previously used to store the data after initialization of the first logical storage unit.

24. The computer program product of claim 23 , wherein said control logic further comprises:

re-initializing said first logical storage unit block after all of said plurality of logical storage unit sections from said first logical storage unit block have been used in said write operations.