Semiconductor device including power-on reset circuit

1. A semiconductor device comprising:

a first device configured to generate a first reset signal when a first signal is applied thereto, the first signal having a first ramp-up time and being one of a plurality of signals having different ramp-up times;

a second device configured to generate a second reset signal when a second signal is applied thereto, the second signal having a second ramp-up time and being one of the plurality of signals; and

a storage unit configured to receive at least one of the first reset signal and the second reset signal.

2. The semiconductor device of claim 1 , wherein the second ramp-up time is longer than the first ramp-up time.

3. The semiconductor device of claim 1 , further comprising:

a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope; and

a first signal generator configured to receive the first voltage and generate the first signal.

4. The semiconductor device of claim 3 , wherein the first signal generator is further configured to turn off the first signal while the first voltage rises at the second slope.

5. The semiconductor device of claim 3 , wherein the first signal generator includes an asymmetric inverter configured to receive the first voltage, invert the first voltage, and generate the first signal that sharply decreases with a rise of the first voltage.

6. The semiconductor device of claim 1 , further comprising:

a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof;

a capacitive unit connected between the output terminal of the voltage divider and the second power supply source; and

a second signal generator connected to the output terminal of the voltage divider and configured to receive the second voltage and generate the second signal.

7. The semiconductor device of claim 1 , further comprising:

an undervoltage-lockout (UVLO) module configured to generate a third signal, the third signal having a third ramp-up time and being one of the plurality of signals, wherein the storage unit is further configured to receive a third reset signal generated by the third signal.

8. The semiconductor device of claim 7 ,

wherein the storage unit is further configured to receive at least one of the first reset signal, the second reset signal, and the third reset signal.

9. The semiconductor device of claim 7 , wherein the second ramp-up time is longer than the first ramp-up time and is shorter than the third ramp-up time.

10. The semiconductor device of claim 7 , wherein the UVLO module comprises:

a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof;

a reference voltage generator configured to generate a reference voltage; and

a comparator configured to compare the second voltage of the output terminal of the voltage divider with the reference voltage and generate the third signal.

11. The semiconductor device of claim 7 , further comprising:

a first signal generator configured to generate the first signal; and

a second signal generator configured to generate the second signal.

12. The semiconductor device of claim 11 , further comprising a voltage divider connected between a first power supply source and a second power supply source.

13. The semiconductor device of claim 12 , wherein the second signal generator and the UVLO module receive a voltage from the voltage divider and generate the second and third signals, respectively.