SYSTEM AND METHOD FOR ON-THE-FLY INCREMENTAL MEMORY REPAIR
A device for repairing a memory device may include spare memory blocks that may replace corresponding memory blocks that include at least one non-operational memory cell. One or more registers may be coupled in a chain to store memory repair information. A memory repair module may identify, upon a power-up test of the memory device, non-operational memory cells, which are incremental to previously identified defective memory cells in previous power-up tests, and may provide corresponding memory repair information of the identified non-operational memory cells. A logic circuit may block access to one or more registers and may facilitate storing, in one or more unblocked registers, the corresponding memory repair information of the identified one or more non-operational memory cells. The memory repair module may swap a memory block including the identified non-operational memory cells with a spare memory block based on content of the one or more unblocked registers.
1 . A device for repairing a memory device, the device comprising:
one or more spare memory blocks configured to replace corresponding one or more memory blocks, each of the one or more memory blocks including at least one non-operational memory cell;
a plurality of registers coupled in a chain and configured to store memory repair information;
a memory repair module configured to identify, upon a power-up test of the memory device, one or more non-operational memory cells, which are incremental to previously identified defective memory cells in previous power-up tests of the memory device, and to provide corresponding memory repair information of the identified one or more non-operational memory cells; and
a logic circuit configured to block access to one or more registers of the plurality of registers, and to facilitate storing, in one or more unblocked registers of the plurality of registers, the corresponding memory repair information of the identified one or more non-operational memory cells,
wherein the memory repair module is configured to swap a memory block including the identified one or more non-operational memory cells with a spare memory block of the one or more spare memory blocks based on content of the one or more unblocked registers of the plurality of registers.
2 . The device of claim 1 , wherein the one or more spare memory blocks comprise at least one of a spare memory row or a spare memory column.
3 . The device of claim 1 , wherein the plurality of registers comprises already existing built-in-self-repair (BISR) registers.
4 . The device of claim 1 , wherein each register of the plurality of registers is associated with a memory block, and wherein the content of the one or more unblocked registers of the plurality of registers comprise addresses of spare memory blocks available for incremental repair.
5 . The device of claim 1 , wherein the memory repair information comprises address information corresponding to non-operational memory cells.
6 . The device of claim 1 , wherein the logic circuit is configured to block access to the one or more registers of the plurality of registers if content of one or more registers of the plurality of registers is non-zero, indicating that a corresponding spare block of an associated memory block is unavailable.
7 . The device of claim 1 , wherein the memory repair module is configured to repair the memory device on-the fly while the memory device is in a normal mode of operation.
8 . A method for repairing a memory device, the method comprising:
using one or more spare memory blocks to replace corresponding one or more memory blocks each including at least one non-operational memory cell;
storing memory repair information in a plurality of registers coupled in a chain;
identifying, upon a power-up test of the memory device, one or more non-operational memory cells, which are incremental to previously identified defective memory cells in previous power-up tests of the memory device;
providing corresponding memory repair information of the identified one or more non-operational memory cells;
blocking access to one or more registers of the plurality of registers;
facilitating storing, in one or more unblocked registers of the plurality of registers, the corresponding memory repair information of the identified one or more non-operational memory cells; and
swapping a memory block including the identified one or more non-operational memory cells with a spare memory block of the one or more spare memory blocks based on content of the one or more unblocked registers of the plurality of registers.
9 . The method of claim 8 , wherein using the one or more spare memory blocks comprises using at least one of a spare memory row or a spare memory column.
10 . The method of claim 8 , wherein storing the memory repair information in the plurality of registers comprises storing the memory repair information in already existing BISR registers.
11 . The method of claim 8 , wherein each register of the plurality of registers is associated with a memory block, and wherein the content of the one or more unblocked registers of the plurality of registers comprise addresses of spare memory blocks available for incremental repair.
12 . The method of claim 8 , wherein providing the corresponding memory repair information comprises providing address information corresponding to the non-operational memory cells.
13 . The method of claim 8 , wherein blocking access to the one or more registers of the plurality of registers is performed if content of one or more registers of the plurality of registers is non-zero, indicating that a corresponding spare block of an associated memory block is unavailable.
14 . The method of claim 8 , further comprising repairing the memory device on-the fly and while the memory device is in a normal mode of operation.
15 . A system for on-the-fly repair of a memory device, the system comprising:
memory configured to store one or more program modules; and
one or more processors coupled to the memory and configured to execute the one or more program modules to perform:
using one or more spare memory blocks to replace corresponding one or more memory blocks each including at least one non-operational memory cell;
storing memory repair information in a plurality of registers coupled in a chain;
identifying, upon a power-up test of the memory device, one or more non-operational memory cells, which are incremental to previously identified defective memory cells in previous power-up tests of the memory device;
providing corresponding memory repair information of the identified one or more non-operational memory cells;
blocking access to one or more registers of the plurality of registers;
facilitating storing, in one or more unblocked registers of the plurality of registers, the corresponding memory repair information of the identified one or more non-operational memory cells; and
swapping a memory block including the identified one or more non-operational memory cells with a spare memory block of the one or more spare memory blocks based on content of the one or more unblocked registers of the plurality of registers.
16 . The system of claim 15 , wherein the one or more processors are configured to execute the one or more program modules to use at least one of a spare memory row or a spare memory column to replace the corresponding one or more memory blocks each including the at least one non-operational memory cells.
17 . The system of claim 15 , wherein the one or more processors are configured to execute the one or more program modules to store the memory repair information in already existing BISR registers.
18 . The system of claim 15 , wherein each register of the plurality of registers is associated with a memory block, and wherein the content of the one or more unblocked registers of the plurality of registers comprise addresses of spare memory blocks available for incremental repair.
19 . The system of claim 15 , wherein the one or more processors are configured to execute the one or more program modules to provide address information corresponding to the non-operational memory cells.
20 . The system of claim 15 , wherein the one or more processors are configured to execute the one or more program modules to block access to the one or more registers of the plurality of registers if content of one or more registers of the plurality of registers is non-zero, indicating that a corresponding spare block of an associated memory block is unavailable.