Method of erase state handling in flash channel tracking
View Patent ↗An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters.
1. An apparatus comprising:
a non-volatile memory; and
a controller configured to track one or more channel statistics of the non-volatile memory, wherein the controller estimates a current erase state voltage distribution of the non-volatile memory by selecting one or more parameters of a pre-characterized erase state voltage distribution from a look-up table based upon at least one of the one or more channel statistics tracked by the controller.
2. The apparatus according to claim 1 , wherein the one or more channel statistics comprise a statistical parameter indicating a number of program and erase cycles, a statistical parameter indicating a retention time, a statistical parameter indicating an amount of write disturb, and a statistical parameter indicating an amount of read disturb.
3. The apparatus according to claim 1 , wherein the one or more parameters of the pre-characterized erase state voltage distribution comprise pre-determined mean and variance values.
4. The apparatus according to claim 1 , wherein the one or more parameters of the pre-characterized erase state voltage distribution comprise mean and standard deviation values.
5. The apparatus according to claim 1 , wherein the look-up table associates a respective set of parameters of the pre-characterized erase state voltage distribution with each of a plurality of values of the one or more channel statistics.
6. The apparatus according to claim 1 , wherein the controller is further configured to perform error correction on data read from the non-volatile memory using a soft decode error correction code.
7. The apparatus according to claim 6 , wherein the soft decode error correction code comprises a low density parity check code.
8. The apparatus according to claim 6 , wherein the controller is configured to calculate one or more soft decisions based on the one or more parameters of the pre-characterized erase state voltage distribution selected from the look-up table.
9. The apparatus according to claim 8 , wherein the soft decisions comprise a log likelihood ratio (LLR).
10. The apparatus according to claim 1 , wherein the non-volatile memory and the controller are part of a solid state drive (SSD).
11. A method of erase state handling in flash channel tracking comprising:
tracking one or more channel statistics of a non-volatile memory; and
estimating a current erase state voltage distribution of the non-volatile memory by selecting one or more parameters of a pre-characterized erase state voltage distribution from a look-up table based upon at least one of the one or more channel statistics.
12. The method according to claim 11 , wherein the one or more channel statistics comprise a statistical parameter indicating a number of program and erase cycles, a statistical parameter indicating a retention time, a statistical parameter indicating an amount of write disturb, and a statistical parameter indicating an amount of read disturb.
13. The method according to claim 11 , wherein the one or more parameters of the pre-characterized erase state voltage distribution comprise pre-determined mean and variance values.
14. The method according to claim 11 , wherein the one or more parameters of the pre-characterized erase state voltage distribution comprise mean and standard deviation values.
15. The method according to claim 11 , wherein the look-up table associates a respective set of parameters of the pre-characterized erase state voltage distribution with each of a plurality of values of the one or more channel statistics.
16. The method according to claim 11 , further comprising:
calculating a log likelihood ratio (LLR) based upon the one or more parameters of the pre-characterized erase state voltage distribution selected from the look-up table.
17. The method according to claim 11 , further comprising:
estimating a read reference voltage threshold based upon the one or more parameters of the pre-characterized erase state voltage distribution selected from the look-up table.
18. An apparatus comprising;
an interface circuit configured to process a plurality of read/write operations to/from a non-volatile memory; and
a controller circuit configured to track channel statistics of the non-volatile memory, wherein the controller circuit estimates a current erase state voltage distribution of the non-volatile memory by selecting one or more parameters of a pre-characterized erase state voltage distribution from a look-up table based upon at least one of the channel statistics tracked by the controller circuit.
19. The apparatus according to claim 18 , wherein the channel statistics tracked by the controller circuit comprise at least one of a statistical parameter indicating a number of program and erase cycles, a statistical parameter indicating a retention time, a statistical parameter indicating an amount of write disturb, and a statistical parameter indicating an amount of read disturb.
20. The apparatus according to claim 18 , wherein:
the look-up table associates a plurality of parameters descriptive of the pre-characterized erase state voltage distribution with particular values of at least one of the channel statistics tracked by the controller circuit; and
the plurality of parameters descriptive of the pre-characterized erase state voltage distribution comprise one or more of a pre-determined mean value, a pre-determined standard deviation value, and a pre-determined variance value for each particular value of the at least one of the channel statistics tracked by the controller circuit.