Three-dimensional integrated circuit laminate, and interlayer filler for three-dimensional integrated circuit laminate
View Patent ↗To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property, a three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (A) and an organic filler (B) and having a thermal conductivity of at least 0.8 W/(rrrK) between the semiconductor substrate.
1. A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, has a first interlayer filler layer containing a resin (A) and an inorganic filler (B) and having a thermal conductivity of at least 0.8 W/(m·K) between the semiconductor substrates, and has a second interlayer filler layer coma a resin (a) and an inorganic filler (b) is formed between the semiconductor substrate laminate and the organic substrate, wherein the semiconductor substrate laminate is mounted on an organic substrate, said first interlayer filler layer is obtained from a composition containing from 50 to 400 parts by weight of an inorganic filler (B), from 0.1 to 60 parts by weight of a curing agent (C) and from 0.1 to 10 parts by weight of a flux (D) per 100 parts by weight of a resin (A), the resin (A) is a plurality of epoxy resins differing in the structural units in combination, and the inorganic filler (B) has an average particle size of at least 0.1 μm and at most 10 μm, a maximum particle size of at most 10 μm, and a thermal conductivity of at least 2 W/(m·K).
2. The three-dimensional integrated circuit laminate according to claim 1 , wherein the coefficient of linear thermal expansion of the first interlayer filler layer is at least 3 ppm/K and at most 70 ppm/K.
3. The three-dimensional integrated circuit laminate according to claim 1 , wherein the dielectric constant of the inorganic filler (B) contained in the first interlayer filler layer is at most 6.
4. A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, has a first interlayer filler layer containing a resin (A) and an inorganic filler (B) and having a coefficient of linear thermal expansion of at least 3 ppm/K and at most 70 ppm/K between the semiconductor substrates, and has a second interlayer filler layer containing a resin (a) and an inorganic filler (b) is formed between the semiconductor substrate laminate and the organic substrate, wherein the semiconductor substrate laminate is mounted on an organic substrate, and the inorganic filler (B) having an average particle size of at least 0.1 μm and at most 10 μm and a maximum particle size of 10 μm, wherein said first interlayer filler layer is obtained from a composition containing from 50 to 400 parts by weight of an inorganic filler (B), from 0.1 to 60 parts by weight of a curing agent (C) and from 0.1 to 10 parts by weight of a flux (D) per 100 parts by weight of a resin (A), the resin (A) is a plurality of epoxy resins differing in the structural units in combination, and the inorganic filler (B) has an average particle size of at least 0.1 μm and at most 10 μm, a maximum particle size of at most 10 μm, and a thermal conductivity of at least 2 W/(m·K).
5. A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, has a first interlayer filler layer containing a resin (A) and an inorganic filler (B) between the semiconductor substrates, and has a second interlayer filler layer containing a resin (a) and an inorganic filler (b) is formed between the semiconductor substrate laminate and the organic substrate, wherein the semiconductor substrate laminate is mounted on an organic substrate, and the inorganic filler (B) having an average particle size of at least 0.1 μm and at most 10 μm, a maximum particle size of 10 μm, and a dielectric constant of at most 6, wherein said first interlayer filler layer is obtained from a composition containing from 50 to 400 parts by weight of an inorganic filler (B), from 0.1 to 60 parts by weight of a curing agent (C) and from 0.1 to 10 parts by weight of a flux (D) per 100 parts by weight of a resin (A), the resin (A) is a plurality of epoxy resins differing in the structural units in combination, and the inorganic filler (B) has an average particle size of at least 0.1 μm and at most 10 μm, a maximum particle size of at most 10 μm, and a thermal conductivity of at least 2 W/(m·K).
6. The three-dimensional integrated circuit laminate according to claim 1 , wherein the specific surface area of the inorganic filler (B) contained in the first interlayer filler layer between the semiconductor substrates is at least 1 m 2 /g and at most 60 m 2 /g.
7. The three-dimensional integrated circuit laminate according to claim 1 , wherein the semiconductor substrates are silicon substrates.
8. The three-dimensional integrated circuit laminate according to claim 1 , wherein of the inorganic filler (B), the average particle size is at least 0.2 μm and at most 5 μm, and the specific surface area is at least 1 m 2 /g and at most 25 m 2 /g.
9. The three-dimensional integrated circuit laminate according to claim 1 , wherein the inorganic filler (B) is boron nitride.
10. The three-dimensional integrated circuit laminate according to claim 1 , wherein the thickness of the first interlayer filler layer is at least 1 μm and at most 50 μm.
11. The three-dimensional integrated circuit laminate according to claim 1 , which has solder connection terminals for electric signal connection between the semiconductor substrates each having a semiconductor device layer formed thereon in the first interlayer filler layer.
12. The three-dimensional integrated circuit laminate according to claim 1 , wherein the organic substrate has a multilayer circuit structure having a wiring layer containing copper in a resin plate containing an epoxy resin as a resin component.
13. The three-dimensional integrated circuit laminate according to claim 1 , wherein the second interlayer filler layer contains the inorganic filler (b) in an amount of at least 50 parts by weight and at most 400 parts by weight per 100 parts by weight of the resin (a).
14. The three-dimensional integrated circuit laminate according to claim 1 , wherein the coefficient of linear thermal expansion of the second interlayer filler layer is at least 10 ppm/K and at most 50 ppm/K.
15. The three-dimensional integrated circuit laminate according to claim 1 , wherein the dielectric constant of the second interlayer filler layer is at most 6.
16. The three-dimensional integrated circuit laminate according to claim 1 , wherein the inorganic filler (b) has an average particle size of at least 0.1 μm and at most 20 μm, a maximum particle size of 30 μm, a specific surface area of at least 1 m2/g and at most 60 m2/g, a thermal conductivity of at least 1 W/(m·K), and a dielectric constant f at most 6.
17. The three-dimensional integrated circuit laminate according to claim 1 , wherein the resin (A) is a plurality of epoxy resins containing at least a phenoxy resin and differing in the structural units in combination.
18. The three-dimensional integrated circuit laminate according to claim 1 , wherein thickness of the second interlayer filler layer is at least 50 μm and at most 300 μm.
19. The three-dimensional integrated circuit laminate according to claim 1 , wherein the first interlayer filler layer and the second interlayer filler layer have a different composition.
20. The three-dimensional integrated circuit laminate according to claim 4 , wherein the first interlayer filler layer and the second interlayer filler layer have a different composition.
21. The three-dimensional integrated circuit laminate according to claim 5 , wherein the first interlayer filler layer and the second interlayer filler layer have a different composition.
22. The three-dimensional integrated circuit laminate according to claim 1 , wherein the flux (D) has a melt temperature of from 90° C. to 220° C.
23. The three-dimensional integrated circuit laminate according to claim 4 , wherein the flux (D) has a melt temperature of from 90° C. to 220° C.
24. The three-dimensional integrated circuit laminate according to claim 5 , wherein the flux (D) has a melt temperature of from 90° C. to 220° C.