IP Library Granted Patent US 9,076,905
Granted Patent B2
US 9,076,905 · App. 14/041,907 · Granted Jul 7, 2015

Semiconductor device and method for manufacturing the same

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Quick Facts
Patent No.
US 9,076,905
App. No.
14/041,907
Granted
Jul 7, 2015
Kind
B2
Abstract

A semiconductor device includes a substrate and a first insulating layer. The first insulating layer includes a first lower layer and a first upper layer on the first lower layer. The first insulating layer has a first opening through the first lower layer and the first upper layer. A maximum width of the first opening at the first lower layer is different from a maximum width of the first opening at the first upper layer.

Claims (26)

1. A method for manufacturing a semiconductor device comprising:

forming a lower insulating layer on at least one of a front surface and a back surface of a substrate;

forming an upper insulating layer on the lower insulating layer; and

forming an opening passing through the upper insulating layer and the lower insulating layer,

wherein a maximum width of the opening at the lower insulating layer is greater than a maximum width of the opening at the upper insulating layer, and

wherein the forming of the opening includes:

a first etching step of dry etching the upper insulating layer using a laser; and

a second etching step of wet etching the lower insulating layer using the upper insulating layer as a mask.

2. The method of claim 1 , wherein a width of the opening at a lower portion of the lower insulating layer is greater than a width of the opening at a lower portion of the upper insulating layer.

3. The method of claim 2 , wherein a width of the opening at an upper portion of the lower insulating layer is greater than the width of the opening at the lower portion of the lower insulating layer.

4. The method of claim 3 , wherein a side surface of the opening connecting the upper portion of the lower insulating layer to the lower portion of the lower insulating layer is in the form of a curved line.

5. The method of claim 2 , wherein a width of the opening at an upper portion of the lower insulating layer is greater than the width of the opening at the lower portion of the upper insulating layer.

6. The method of claim 1 , wherein the second etching step includes removing particles generated in the first etching step.

7. The method of claim 1 , wherein the lower insulating layer and the upper insulating layer are formed only on the front surface of the substrate.

8. The method of claim 7 , further comprising, before forming the lower insulating layer on the front surface of the substrate, forming an emitter layer at the front surface of the substrate.

9. The method of claim 8 , further comprising, before forming the emitter layer at the front surface of the substrate, texturing the front surface of the substrate.

10. The method of claim 7 , wherein the lower insulating layer is formed of aluminum oxide or silicon oxide, and the upper insulating layer is formed of silicon oxide.

11. The method of claim 1 , wherein the lower insulating layer and the upper insulating layer are formed on both the front surface and the back surface of the substrate.

12. The method of claim 11 , further comprising, before forming the lower insulating layer on the front surface of the substrate, forming an emitter layer at the front surface of the substrate.

13. The method of claim 12 , further comprising, before forming the emitter layer at the front surface of the substrate, texturing the front surface of the substrate.

14. The method of claim 12 , further comprising, before forming the lower insulating layer on the back surface of the substrate, forming a back surface field layer at the back surface of the substrate.

15. The method of claim 14 , further comprising, before forming the back surface field layer at the back surface of the substrate, texturing the back surface of the substrate.

16. The method of claim 11 , wherein the lower insulating layer on the front surface of the substrate and the lower insulating layer on the back surface of the substrate are simultaneously formed of the same material.

17. The method of claim 16 , wherein the lower insulating layer on the front surface of the substrate and the lower insulating layer on the back surface of the substrate are formed of aluminum oxide or silicon oxide.

18. The method of claim 11 , wherein the upper insulating layer on the front surface of the substrate and the upper insulating layer on the back surface of the substrate are simultaneously formed of the same material.

19. The method of claim 18 , wherein the upper insulating layer on the front surface of the substrate and the lower insulating layer on the back surface of the substrate are formed of silicon nitride.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2024
From: SHANGRAO XINYUAN YUEDONG TECHNOLOGY DEVELOPMENT CO. LTD.
To: TRINA SOLAR CO., LTD.
Reel/Frame 066831/0802 →
CHANGE OF NAME Recorded Dec 19, 2023
From: SHANGRAO JINKO SOLAR TECHNOLOGY DEVELOPMENT CO., LTD
To: SHANGRAO XINYUAN YUEDONG TECHNOLOGY DEVELOPMENT CO. LTD
Reel/Frame 066078/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2022
From: LG ELECTRONICS INC.
To: SHANGRAO JINKO SOLAR TECHNOLOGY DEVELOPMENT CO., LTD
Reel/Frame 061572/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2013
From: JIN, YOONSIL; SHIM, GOOHWAN; PARK, CHANGSEO; CHOE, YOUNGHO
To: LG ELECTRONICS INC.
Reel/Frame 031311/0389 →