FIELD EFFECT TRANSISTOR HAVING A TROUGH CHANNEL
The present invention is directed to a field effect transistor having a trough channel structure. The transistor comprises a semiconductor substrate of a first conductivity type having a trough structure therein with the trough structure extending along a first direction; an insulating layer formed on top of the trough structure; a gate formed on top of the insulator layer in a second direction perpendicular to the first direction and extending over and into the trough structure with a gate dielectric layer interposed therebetween; a source and a drain of a second conductivity type opposite to the first conductivity type formed in the trough structure on opposite sides of the gate.
1 . A field effect transistor device comprising:
a semiconductor substrate of a first conductivity type having a trough structure therein, said trough structure extending along a first direction;
an insulating layer formed on top of said trough structure;
a gate formed on top of said insulator layer in a second direction perpendicular to said first direction and extending over and into said trough structure with a gate dielectric layer interposed therebetween;
a source of a second conductivity type opposite to said first conductivity type formed in said trough structure on one side of said gate; and
a drain of said second conductivity type formed in said trough structure on other side of said gate.
2 . The transistor device according to claim 1 , further comprising a channel of said first conductivity type between said source and drain in said trough structure.
3 . The transistor device according to claim 1 , further comprising a contact stud formed on top of each of said source and drain.
4 . The transistor device according to claim 1 , wherein said first conductivity type is p type and said second conductivity type is n type.
5 . The transistor device according to claim 1 , wherein said first conductivity type is n type and said second conductivity type is p type.
6 . The transistor device according to claim 1 , wherein said semiconductor substrate comprises silicon.
7 . The transistor device according to claim 1 , wherein said gate dielectric layer comprises silicon oxide.
8 . The transistor device according to claim 1 , wherein said gate dielectric layer is formed of a compound comprising hafnium and oxygen
9 . The transistor device according to claim 1 , wherein said gate electrode comprises doped polysilicon.
10 . The transistor device according to claim 1 , wherein said gate includes at least one layer formed of titanium nitride.
11 . The transistor device according to claim 1 , wherein said insulating layer is formed of silicon oxide, silicon nitride, or silicon oxynitride.
12 . The transistor device according to claim 1 , wherein said insulating layer partially covers top of said trough structure to form two ledges on top of said trough structure.
13 . A method for manufacturing the transistor device of claim 1 , the method comprising the steps of:
providing a semiconductor substrate having a first type conductivity;
depositing an insulating layer on top of said semiconductor substrate;
forming a trough structure in said semiconductor substrate;
forming a gate dielectric layer on the surface of said trough structure;
forming a gate on top of said insulating layer, said gate extending over and into said trough structure with said gate dielectric layer interposed therebetween; and
forming a source and a drain having a second conductivity type opposite to said first conductivity type in said trough structure by ion implantation using said gate as a mask.
14 . The method according to claim 13 , wherein said first conductivity type is p type and said second conductivity type is n type.
15 . The method according to claim 13 , wherein said first conductivity type is n type and said second conductivity type is p type.
16 . The method according to claim 13 , wherein said semiconductor substrate is formed of silicon and said gate dielectric layer is formed of silicon oxide.
17 . The method according to claim 16 , wherein the step of forming said gate dielectric layer is carried out by thermal oxidation of said trough structure.
18 . A field effect transistor device comprising:
a p-type silicon substrate having a trough structure therein, said trough structure extending along a first direction;
an insulating layer formed on top of said trough structure;
a gate made of doped polysilicon formed on top of said insulator layer in a second direction perpendicular to said first direction and extending over and into said trough structure with a gate oxide layer interposed therebetween;
a source having an n-type conductivity formed in said trough structure on one side of said gate; and
a drain having said n-type conductivity formed in said trough structure on other side of said gate.
19 . The transistor device according to claim 18 , further comprising a channel having said p-type conductivity between said source and drain in said trough structure.
20 . The transistor device according to claim 18 , further comprising a contact stud formed on top of each of said source and drain.