Variable resistance memory device and method of manufacturing the same
View Patent ↗A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate, a lower electrode formed in a bottom of each of the holes, a first spacer formed on the lower electrode and a sidewall of each of the holes, a second spacer formed on an upper sidewall of the first spacer, a third spacer formed on a lower sidewall of the first spacer below the second spacer, a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole, and an upper electrode formed on the variable resistance part to be buried in each hole.
1. A method of manufacturing a variable resistance memory device, the method comprising:
forming a multi-layered insulating layer on a semiconductor substrate;
forming a hole exposing a portion of an upper surface of the semiconductor substrate by etching the multi-layered insulating layer;
forming a lower electrode in a bottom of the hole;
forming a first spacer on the lower electrode and a sidewall of the hole;
forming a second spacer on an upper sidewall of the first spacer;
forming a third spacer on a lower sidewall of the first spacer;
forming a variable resistance part in the hole to have a height lower than that of the hole; and
forming an upper electrode on the variable resistance part to be buried in the hole.
2. The method of claim 1 , wherein the multi-layered insulating layer includes:
a first insulating layer formed on the lower electrode and formed of nitride;
a second insulating layer formed on the first insulating layer and formed of oxide;
a third insulating layer formed on the second insulating layer and formed of the nitride; and
a fourth insulating layer formed on the third insulating layer and formed of the oxide.
3. The method of claim 2 , wherein the fourth insulating layer is removed using the third insulating layer as an etch stopper layer in the forming of the upper electrode.
4. The method of claim 3 , wherein the second spacer is formed by oxidizing the first spacer in the forming of the second spacer.
5. The method of claim 4 , further comprising a sacrificial layer having a certain height in the hole after the forming of the first spacer.
6. The method of claim 5 , further comprising removing the sacrificial layer after the forming of the second spacer.
7. The method of claim 6 , wherein a height of the variable resistance part is formed to be higher than that of the third spacer in the forming of the variable resistance part.
8. A method of manufacturing a variable resistance memory device, the method comprising:
forming a multi-layered insulating layer on a semiconductor substrate;
forming a hole exposing a portion of an upper surface of the semiconductor substrate by etching the multi-layered insulating layer;
forming a lower electrode in a bottom of the hole;
forming a first spacer on the lower electrode and a sidewall of the hole;
forming a second spacer protruded from an upper sidewall of the first spacer;
depositing a third spacer material into the hole;
forming a third spacer on a lower sidewall of the first spacer and below the second spacer by selectively etching the third spacer material; and
forming a variable resistance part in the hole to have a height lower than that of the hole.
9. The method of claim 8 , further comprising forming an upper electrode on the variable resistance part to be buried in the hole.
10. The method of claim 9 , wherein the second spacer is formed by oxidizing the first spacer in the forming of the second spacer.
11. The method of claim 10 , wherein the multi-layered insulating layer includes:
a first insulating layer formed on the lower electrode and formed of nitride;
a second insulating layer formed on the first insulating layer and formed of oxide;
a third insulating layer formed on the second insulating layer and formed of the nitride; and
a fourth insulating layer formed on the third insulating layer and formed of the oxide.
12. The method of claim 11 , wherein the third spacer material is nitride.