IP Library Granted Patent US 9,424,131
Granted Patent B2
US 9,424,131 · App. 14/045,102 · Granted Aug 23, 2016

Spatially decoupled redundancy schemes for a solid state drive (SSD)

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Quick Facts
Patent No.
US 9,424,131
App. No.
14/045,102
Granted
Aug 23, 2016
Kind
B2
Abstract

An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to write user data using a redundancy scheme. Information about the redundancy is (i) stored in a location separate from the data and (ii) used to recover potentially corrupted user data.

Claims (28)

1. An apparatus comprising:

a non-volatile memory configured to process a plurality of read/write operations, said non-volatile memory comprising a plurality of memory modules each having a size less than a total size of said non-volatile memory; and

a controller configured to write user data and corresponding redundancy data using a data striping redundancy scheme, separate a first memory location comprising the user data and a second memory location comprising the redundancy data by mapping the user data to external logical block addresses (LBAs) and the redundancy data to internal LBAs, and use the redundancy data to recover potentially corrupted user data.

2. The apparatus according to claim 1 , wherein said first memory location is on a first memory module, said second memory location is on a second memory module, and said second memory module is separate from said first memory module.

3. The apparatus according to claim 1 , wherein a map mapping said external LBAs and said internal LBAs to physical memory is updated each time said user data and said redundancy data are written.

4. The apparatus according to claim 3 , wherein said apparatus comprises a Solid State Drive (SSD), and wherein a physical location of the map within the SSD changes each time the map is updated.

5. The apparatus according to claim 3 , wherein said redundancy data includes redundancy information and metadata, said redundancy information protecting said user data, said metadata specifying a set of blocks written according to a data stripe (S-block) and associated with the redundancy information.

6. The apparatus according to claim 5 , wherein said map includes a physical address and a length corresponding to the set of blocks, wherein said metadata includes bitmap data indicating one or more pages contributing to said redundancy information, and wherein said one or more pages comprise logical page (L-page) data.

7. The apparatus according to claim 6 , wherein a logical page (L-page) of the L-page data can reside completely inside a page or start in one page and end in another page.

8. The apparatus according to claim 1 , wherein said redundancy data is calculated after each new write.

9. The apparatus according to claim 1 , wherein said redundancy scheme is implemented with over-provisioning capacity available on a portion of a memory module of the plurality of memory modules that is accessible by said controller using said internal LBAs, said internal LBAs being outside a range of said external LBAs, said external LBAs being used by a host for normal input/output (I/O) operations.

10. The apparatus according to claim 9 , wherein said plurality of memory modules comprises NAND flash modules, and wherein said over-provisioning capacity is used to store said redundancy data.

11. The apparatus according to claim 1 , wherein said external LBAs or said internal LBAs comprise a logical page number (LPN) and a logical offset.

12. A method for decoupling redundancy data from user data in a storage device, comprising the steps of:

processing a plurality of read/write operations in a non-volatile memory comprising a plurality of memory modules each having a size less than a total size of said non-volatile memory;

writing user data and redundancy data corresponding to said user data using a data striping redundancy scheme;

separating said user data and said redundancy data using external logical block addresses (LBAs) for said user data and internal LBAs for said redundancy data, wherein said redundancy data is (i) stored in a first location of said non-volatile memory separate from a second location of said non-volatile memory used to store said user data and (ii) used to recover potentially corrupted user data.

13. The method according to claim 12 , wherein said first location is a map location on a first memory module, said second location is on a second memory module, said first memory module is separate from said second memory module.

14. The method according to claim 13 , wherein said map location is updated each time said user data is written.

15. The method according to claim 14 , wherein updating said map location each time said user data is written comprises storing mapping information about said redundancy data to a new map location within a Solid State Drive (SSD).

16. The method according to claim 14 , wherein each time said map location is updated a physical location of said redundancy data will change.

17. An apparatus comprising:

a non-volatile memory; and

a controller in communication with a host, said controller configured to:

implement a plurality of data writes, said plurality of data writes including a user data write to write user data received from the host and a redundant data write to write redundant data to protect said user data, wherein at least said user data write includes a data striping write, wherein the plurality of data writes are implemented using a multi-level redundancy scheme, wherein at least one redundancy level of said multi-level redundancy scheme separates the user data from the redundant data using external logical block addresses (LBAs) for the user data and internal LBAs for the redundancy data.

18. The apparatus according to claim 17 , wherein said redundancy data is useable to recover potentially corrupted user data and includes a bitmap to indicate a portion of user data contributing to said redundant data, and wherein a second redundancy level of the multi-level redundancy scheme includes an error-correcting code.

19. The apparatus according to claim 17 , wherein the at least one redundancy level of the multi-level redundancy scheme protects data within a page using erasure-correction code and a second redundancy level of the multi-level redundancy scheme protects the block or the page using error-correction code.

20. The apparatus according to claim 17 , wherein said redundant data is stored to a mapped location physically separate and independent of a location used to store said user data, said mapped location is accessed using said internal LBAs, said internal LBAs being outside a range of the external LBAs.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2013
From: TANG, ALEX G.; BARYUDIN, LEONID
To: LSI CORPORATION
Reel/Frame 031337/0978 →