Mux-based digital delay interpolator

1. A digital delay interpolator comprising:

at least one array of multiplexers, each multiplexer configured to

be input with first and second input voltages, one of the first and second input voltages being a delayed replica of the other input voltage, and

receive a respective selection signal;

a plurality of output lines respectively coupled to said at least one array of multiplexers; and

an output terminal configured to be coupled in common to said plurality of output lines and output a signal delayed by a time delay value based upon a total output capacitance of a number of multiplexers in said at least one array of multiplexers;

each multiplexer of said at least one array thereof being configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.

2. The digital delay interpolator of claim 1 wherein said at least one array of multiplexers comprises a single array of multiplexers to define a single-stage digital delay interpolator.

3. The digital delay interpolator of claim 1 wherein said at least one array of multiplexers comprises a first set, and a second set; wherein each multiplexer of said first set comprises a first input terminal configured to receive the first input voltage, and a second input terminal configured to receive the second input voltage; and wherein each multiplexer of said second set comprises a first input terminal configured to receive the second input voltage, and a second input terminal configured to receive the first input voltage.

4. The digital delay interpolator of claim 1 wherein said at least one array of multiplexers comprises identical multiplexers.

5. The digital delay interpolator of claim 1 wherein said array of multiplexers is coupled in parallel.

6. The digital delay interpolator of claim 1 wherein said output terminal is configured to output the signal delayed by the time delay value without using inverters.

7. A multi-stage digital delay interpolator comprising:

an input phase mixing stage comprising

first and second arrays of multiplexers, each multiplexer configured to

be input with first and second input voltages, one of the first and second input voltages being a delayed replica of the other input voltage, and

receive a respective selection signal;

a plurality of output lines respectively coupled to said first and second arrays of multiplexers,

first and second output terminals,

each multiplexer being configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal, and

a first multiplexer of said first array and a first multiplexer of said second array being configured to output the first input voltage and said second input voltage, respectively,

corresponding multiplexers of said first array and said second array being configured to be controlled by same selection signals,

the respective output lines of the multiplexers of said first array configured to be coupled in common to said first output terminal, and the respective output lines of the multiplexers of said second array configured to be coupled in common to said second output terminal; and

an output phase mixing stage coupled in a cascade with said input phase mixing stage and comprising

a third output terminal,

an array of multiplexers, and

a plurality of output lines respectively coupled to said array of multiplexers,

each multiplexer configured to

be input with first and second output voltages of a preceding phase mixing stage in the cascade,

receive a respective selection signal,

output on the respective output line one of the first and the second output voltages of the preceding phase mixing stage based upon a logic value of the respective selection signal, said plurality of output lines being coupled in common to said third output terminal,

said third output terminal configured to output a signal delayed by a time delay value based upon a total output capacitance of a number of multiplexers in said array of multiplexers.

8. The multi-stage digital delay interpolator of claim 7 further comprising:

at least one intermediate mixing stage coupled in the cascade between said input phase mixing stage and said at least one output phasing mixing stage and including first and second arrays of multiplexers, each multiplexer of said at least one intermediate mixing stage comprising first and second input terminals configured to receive first and second output voltages of said input phase mixing stage, respectively or vice versa;

a plurality of output lines respectively coupled to said first and second arrays of multiplexers of said at least one intermediate mixing stage;

each multiplexer of said first and second arrays of said at least one intermediate mixing stage configured to

receive a respective selection signal, and

selectively output on the respective output line one of said first or second output voltages of said input phase mixing stage based upon a logic value of the respective selection signal;

first and second output terminals,

the respective output lines of the multiplexers of said first array configured to be coupled in common to said first output terminal, and the respective output lines of the multiplexers of said second array configured to be coupled in common to said second output terminal.

9. The multi-stage digital delay interpolator of claim 7 wherein each multiplexer of said first array comprises a first input terminal configured to receive the first input voltage, and a second input terminal configured to receive the second input voltage; and wherein each multiplexer of said second array comprises a first input terminal configured to receive the second input voltage, and a second input terminal configured to receive the first input voltage.

10. The multi-stage digital delay interpolator of claim 7 wherein said array of multiplexers of said output phase mixing stage comprises a first set, and a second set; wherein each multiplexer of said first set comprises a first input terminal configured to receive the first output voltage of the preceding phase mixing, and a second input terminal configured to receive the second output voltage of the preceding phase mixing; and wherein each multiplexer of said second set comprises a first input terminal configured to receive the second output voltage of the preceding phase mixing, and a second input terminal configured to receive the first output voltage of the preceding phase mixing.

11. The multi-stage digital delay interpolator of claim 8 wherein each multiplexer of said first array of said input phase mixing stage comprises a first input terminal configured to receive the first input voltage, and a second input terminal configured to receive the second input voltage; wherein each multiplexer of said second array of said input phase mixing stage comprises a first input terminal configured to receive the second input voltage, and a second input terminal configured to receive the first input voltage.

12. The multi-stage digital delay interpolator of claim 8 wherein said at least one intermediate mixing stage comprises a plurality thereof coupled in cascade between said input and output phase mixing stages and such that a first intermediate stage of the cascade is configured to be input with the first and second output voltages of the input phase mixing stage, each successive phase mixing stage of the cascade being configured to be input with first and second output voltages of the preceding phase mixing stage in the cascade.

13. The multi-stage digital delay interpolator of claim 7 wherein said multiplexers are substantially identical to each other.

14. A method of making a digital delay interpolator comprising:

coupling at least one array of multiplexers, each multiplexer to

be input with first and second input voltages, one of the first and second input voltages being a delayed replica of the other input voltage, and

receive a respective selection signal;

coupling a plurality of output lines respectively to the at least one array of multiplexers; and

coupling an output terminal in common to the plurality of output lines, the output terminal to output a signal delayed by a time delay value based upon a total output capacitance of a number of multiplexers in said at least one array of multiplexers;

each multiplexer of the at least one array thereof to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.

15. The method of claim 14 wherein said at least one array of multiplexers comprises a single array of multiplexers to define a single-stage digital delay interpolator.

16. The method of claim 14 wherein the at least one array of multiplexers comprises a first set, and a second set; wherein each multiplexer of the first set comprises a first input terminal to receive the first input voltage, and a second input terminal to receive the second input terminal; and wherein each multiplexer of the second set comprises a first input terminal to receive the second input voltage, and a second input terminal to receive the first input terminal.

17. The method of claim 14 wherein the at least one array of multiplexers comprises identical multiplexers.

18. The method of claim 14 further comprising coupling the at least one array of multiplexers in parallel.

19. The method of claim 14 wherein the output terminal outputs the signal delayed by the time delay value without using inverters.