Adaptive multi-stage slack borrowing for high performance error resilient computing
View Patent ↗Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.
1. A circuit comprising:
a flip-flop having a D input for receiving input data, a set input, a reset input, and a Q output;
a transition detector having an output configured to detect a transition in the input data within a time window;
a first multiplexer having a first input for receiving a global set signal, a second input for receiving the input data, a control input coupled to the output of the transition detector, and an output coupled to the set input of the flip-flop; and
a second multiplexer having a first input for receiving a global reset signal, a second input for receiving inverted input data, a control input coupled to the output of the transition detector, and an output coupled to the reset input of the flip-flop.
2. A circuit comprising:
a first path coupled to an input of a first flip-flop, wherein the first flip-flop includes a first transition detector having a first time window;
a second path coupled between an output of the first flip-flop and an input of a second flip-flop, wherein the second flip-flop includes a second transition detector having a second time window; and
a third path coupled between an output of the second flip-flop and an input of a third flip-flop, wherein the third flip-flop includes a third transition detector having a third time window;
wherein the widths of the first time window, the second time window, and the third time window are different and wherein the circuit is configured to allow the propagation of a signal sequentially through the first path, the first flip-flop, the second path, the second flip-flop, the third path, and the third flip-flop.
3. The circuit of claim 2 wherein the third time window is larger than the second time window, and the second time window is larger than the first time window.
4. The circuit of claim 2 wherein the second time window is twice as wide as the first time window.
5. The circuit of claim 2 wherein the third time window is three times as wide as the first time window.