IP Library Granted Patent US 9,337,420
Granted Patent B2
US 9,337,420 · App. 14/046,403 · Granted May 10, 2016

Variable resistance memory device and method of manufacturing the same

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Quick Facts
Patent No.
US 9,337,420
App. No.
14/046,403
Granted
May 10, 2016
Kind
B2
Abstract

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode and an upper electrode may be formed in the first hole to contact the variable resistance material layer.

Claims (17)

1. A method of manufacturing a variable resistance memory device, the method comprising:

forming a multi-layered insulating layer by alternately forming a first insulating layer and a second insulating layer on a semiconductor substrate, on which a lower electrode is formed;

forming a first hole exposing the lower electrode by etching the multi-layered insulating layer;

forming an oxide layer by oxidizing a portion of the second insulating layer;

removing the oxide layer so that the first insulating layer protrudes toward the inside of the first hole;

forming a spacer material, including a void, in the first hole;

forming a second hole, exposing the lower electrode, by removing a portion of the spacer material to a certain depth of the first hole;

forming a variable resistance material layer in the second hole; and

forming an upper electrode in a portion of the first hole from which the spacer material has been removed.

2. The method of claim 1 , wherein the first insulating layer and the second insulating layer are formed of materials having different etch selectivities from each other.

3. The method of claim 2 , wherein the first insulating layer includes a nitride, and the second insulating layer includes polysilicon.

4. The method of claim 2 , further comprising: between the forming an oxide layer and the forming a spacer material,

entirely removing the oxide layer; and

depositing an oxide material on an inner sidewall of the first hole.

5. The method of claim 2 , wherein the first insulating layer, which protrudes toward the inside of the first hole when a portion of the spacer material is removed, is removed in the forming of the second hole, and

the second hole is formed by the void.

6. The method of claim 5 , wherein the first insulating layer and the spacer material are formed of a same material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2013
From: KIM, MIN SEOK; YOON, HYO SEOB
To: SK HYNIX INC.
Reel/Frame 031349/0933 →