Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission method
View Patent ↗A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.
1. A system, comprising:
a controller comprising a first external terminal outputting an address or a command, a second external terminal related to a data, a third external terminal related to a strobe signal, a fourth external terminal outputting a first chip select signal, a fifth external terminal outputting a second chip select signal, and a sixth external terminal outputting a system clock;
a first semiconductor memory device comprising a first external terminal receiving the address or the command, a second external terminal related to the data, a third external terminal related to the strobe signal, a fourth external terminal receiving the first chip select signal and a fifth external terminal receiving the system clock; and
a second semiconductor memory device comprising a first external terminal receiving the address or the command, a second external terminal related to the data, a third external terminal related to the strobe signal, a fourth external terminal receiving the second chip select signal, and a fifth external terminal receiving the system clock;
wherein the controller is configured to send an information specifying a length of a preamble of the strobe signal, and
wherein the length of preamble of the strobe signal of each of the first and second memory devices can be set with a length shorter than one period of the system clock.
2. The system as claimed in claim 1 , wherein the first and second semiconductor memory devices can receive the system clock with a first frequency or a second frequency, and
wherein the length of the preamble includes first and second lengths corresponding to the first and second frequencies, respectively.
3. The system as claimed in claim 2 , wherein the more the frequency of the system clock is increased, the longer the length of the preamble is.
4. The system as claimed in claim 3 , wherein the larger a CAS latency is, the longer the length of the preamble is.
5. The system as claimed in claim 3 , wherein the length of the preamble is changed enough that the controller includes a gate opening area, which overlaps the length of the preamble, so that the controller can receive the data from one of the first and second memory devices.
6. The system as claimed in claim 1 , wherein the controller sends the information before one of the first and second memory devices communicate the data.
7. A system, comprising:
a controller;
a first semiconductor memory device;
a second semiconductor memory device;
a first signal line coupled to the controller and the first and second semiconductor memory devices to transfer an address or a command from the controller to the first and second semiconductor memory devices;
a second signal line coupled to the controller and the first and second semiconductor memory devices to transfer a data between the controller and the first and second semiconductor memory devices;
a third signal line coupled to the controller and the first and second semiconductor memory devices to transfer a strobe signal between the controller and the first and second semiconductor memory devices;
a fourth signal line coupled to the controller and the first semiconductor memory device to send a first chip select signal from the controller to the first semiconductor memory device;
a fifth signal line coupled to the controller and the second semiconductor memory device to send a second chip select signal from the controller to the second semiconductor memory device; and
a sixth signal line coupled to the controller and the first and second memory device to send a system clock from the controller to the first and second semiconductor memory devices,
wherein the controller is configured to send an information specifying a length of a preamble of the strobe signal, and
wherein the length of preamble of the strobe signal of each of the first and second memory devices can be set with a length shorter than one period of the system clock.
8. The system as claimed in claim 7 , wherein the first and second semiconductor memory devices can receive the system clock with a first frequency or a second frequency, and
wherein the length of the preamble includes first and second lengths corresponding to the first and second frequencies, respectively.
9. The system as claimed in claim 8 , wherein the more the frequency of the system clock is increased, the longer the length of the preamble is.
10. The system as claimed in claim 9 , wherein the larger a CAS latency is, the longer the length of the preamble is.
11. The system as claimed in claim 9 , wherein the length of the preamble is changed enough that the controller includes a gate opening area, which overlaps the length of the preamble, so that the controller can receive the data from one of the first and second memory devices.
12. The system as claimed in claim 7 , wherein the controller sends the information before one of the first and second memory devices communicate the data.