Clock generation system
A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock.
1. A method comprising:
running an oscillator in a free-running mode to generate an output clock;
determining whether a reference clock source is active;
receiving a request from a cellular baseband to enter a calibrate-mode in which the oscillator receives a calibration signal to correct the output clock from a phase-frequency detector;
when the reference clock source is active and responsive to the request;
activating a phase-frequency detector via a calibration mode input;
switching the oscillator to a calibrate-mode in which the oscillator receives a calibration signal to correct the output clock;
determining whether the reference clock source has gone inactive; and
when the reference clock source has gone inactive, placing the oscillator back in the free-running mode.
2. The method of claim 1 , further comprising:
generating the calibration signal from the reference clock source and the output clock.
3. The method of claim 1 , further comprising:
generating additional clocks from the output clock.
4. The method of claim 3 , where the additional clocks include an audio processing reference clock.
5. The method of claim 3 , where the additional clocks include a system reference clock for housekeeping operations.
6. The method of claim 1 , where switching the oscillator to the calibrate-mode comprises:
asserting a mode control input to clock correction circuitry.
7. The method of claim 1 , determining whether the reference clock source is active comprises:
determining whether a cellular communication reference clock is active.
8. The method of claim 1 , further comprising:
determining whether a clock generation setting has been met; and
where switching the oscillator to the calibrate-mode comprises:
switching the oscillator to the calibrate-mode when the clock generation setting has been met.
9. A system comprising:
an oscillator operable to generate an output clock in both a free-running mode and a calibrate-mode;
a mode control input operable to:
select the free-running mode for the oscillator by deactivating a phase-frequency detector; and
select the calibrate-mode for the oscillator by activating the phase-frequency detector; and
control circuitry configured to control the mode control input to set the free-running mode and the calibrate-mode responsive to a reference clock source input.
10. The system of claim 9 , where:
the control circuitry is configured to set the calibrate-mode when the reference clock source provides a reference clock signal.
11. The system of claim 9 , further comprising:
clock correction circuitry coupled to the mode control input; and where:
the mode control input is configured to connect the clock correction circuitry to the oscillator in calibrate-mode and disconnect the clock correction circuitry from the oscillator in free-running mode.
12. The system of claim 9 , where:
the output clock comprises an audio processing clock.
13. The system of claim 9 , where:
the output clock comprises a system reference clock.
14. The system of claim 9 , further comprising:
a memory configured to store a clock generation setting that specifies when the oscillator should be in calibrate-mode.
15. The system of claim 14 , where:
the clock generation setting specifies a cellular communication connection capability setting.
16. The system of claim 15 , where:
the reference clock source input comprises a cellular communication reference clock source input.
17. The system of claim 16 , where:
the control circuitry is configured to activate a reference clock source that generates a reference clock on the reference clock source input, instead of deactivating the reference clock source responsive to the cellular communication connection capability setting.
18. The system of claim 17 , where:
the control circuitry is operable to activate the reference clock source in order to calibrate an audio processing reference clock obtained from the output clock of the oscillator.
19. A system comprising:
clock generation circuitry comprising:
a mode control input;
clock correction circuitry coupled to the mode control input, the clock correction circuitry configured to generate a calibration signal from an output clock and a reference clock; and
an oscillator coupled to the clock correction circuitry, the oscillator configured to generate the output clock;
a reference clock source input coupled to the clock correction circuitry, the reference clock source configured to send the reference clock to the clock correction circuitry; and
a baseband controller configured to:
determine a criterion is met for entering a calibrate-mode in which the oscillator receives the calibration signal from the clock correction circuitry;
determine whether the reference clock source is active;
when the reference clock source is active and responsive to the criterion, set the mode control input to place the oscillator into the calibrate-mode;
determine whether the reference clock source has gone inactive; and
when the reference clock source has gone inactive, set the mode control input to place the oscillator into a free-running mode.
20. The system of claim 19 , where the mode control input is configured to activate a phase frequency detector, an error controller, or both to place the oscillator into the calibrate-mode.