Phase detection method and apparatus for clock recovery

1. A phase detector, comprising:

a calculation unit configured to calculate a phase difference according to a product of receiving power at different moments, so as to perform clock recovery by using the phase difference;

wherein the receiving power is that obtained in sampling input signals at a predefined sampling rate, the predefined sampling rate being 2 times of a symbol rate;

wherein the calculation unit uses the formula below to calculate the phase difference:

s 2n =Σ i=0 2m−1 (−1) i P 2n−i P 2n−i−k ;

where, s denotes the output of the phase detector, subscript 2n denotes a serial number of a sampling point, the predefined sampling rate is 2 times of a symbol rate, P denotes the receiving power, both n and m are positive integers, the number of summation items is 2m, and k denotes the relative delay between the two multiplicative receiving power values, k=0, 1, 2 . . . .

2. The phase detector according to claim 1 , wherein the calculation unit comprises:

a first delay module configured to perform first delay to the receiving power;

a multiplier configured to multiply the receiving power by the receiving power to which the first delay has been performed by the first delay module;

2m−1 second delay modules, each of which being configured to perform second delay to the output of the multiplier or the output of a second delay module preceding the current second delay module; and

a summation module configured to add up the output of the multiplier and the output of each of the second delay modules after being alternatively multiplied by 1 and −1, so as to obtain the phase difference.

3. The phase detector according to any one of claim 1 , wherein

for a single-polarization system, the receiving power is P=I 2 +Q 2 ;

and for a dual-polarization system, the receiving power is P=P x +P y , P x =I x 2 +Q x 2 , P y =I y 2 +Q y 2 ;

where, I is a sampling value of an I-th component of a received signal, Q is a sampling value of a Q-th component of the received signal, P x is the receiving power of the received signal at x polarization state, P y is the receiving power of the received signal at y polarization state, I x is a sampling value of the I-th component of the received signal at x polarization state, Q x is a sampling value of the Q-th component of the received signal at x polarization state, I y is a sampling value of the I-th component of the received signal at y polarization state, and Q y is a sampling value of the Q-th component of the received signal at y polarization state.

4. A clock recovery apparatus, comprising:

a voltage controlled oscillator configured to drive an analog-digital converter for sampling; and

a phase detector connected to the voltage controlled oscillator and configured to detect a phase difference,

wherein the phase detector comprises a calculation unit which is configured to calculate a phase difference according to a product of receiving power at different moments, so as to perform clock recovery by using the phase difference, wherein the receiving power is that obtained in sampling input signals at a predefined sampling rate, the predefined sampling rate being 2 times of a symbol rate;

wherein the calculation unit uses the formula below to calculate the phase difference:

s 2n =Σ i=0 2m−1 (−1) i P 2n−i P 2n−i−k ;

where, s denotes the output of the phase detector, subscript 2n denotes a serial number of a sampling point, the predefined sampling rate is 2 times of a symbol rate, P denotes the receiving power, both n and m are positive integers, the number of summation items is 2m, and k denotes the relative delay between the two multiplicative receiving power values, k=0, 1, 2 . . . .

5. A single-polarization digital coherent receiver, comprising:

a coherent detector configured to convert a received optical signal into an electrical signal;

an analog-digital converter connected to the coherent detector and configured to perform analog-digital conversion to an I-th component and Q-th component of the received signal outputted by the coherent detector;

a dispersion compensator connected to the analog-digital converter and configured to perform dispersion compensation to the received signal outputted by the analog-digital converter;

a data recovery apparatus connected to the dispersion compensator and configured to perform data recovery to the received signal to which dispersion compensation has been performed by the dispersion compensator; and

a clock recovery apparatus comprising a voltage controlled oscillator and a phase detector, the voltage controlled oscillator is configured to drive an analog-digital converter for sampling, the phase detector is connected to the voltage controlled oscillator and configured to detect a phase difference,

wherein the phase detector comprises a calculation unit which is configured to calculate a phase difference according to a product of receiving power at different moments, so as to perform clock recovery by using the phase difference, wherein the receiving power is that obtained in sampling input signals at a predefined sampling rate, the predefined sampling rate being 2 times of a symbol rate, wherein the calculation unit uses the formula below to calculate the phase difference:

s 2n =Σ i=0 2m−1 (−1) i P 2n−i P 2n−i−k ;

where, s denotes the output of the phase detector, subscript 2n denotes a serial number of a sampling point, the predefined sampling rate is 2 times of a symbol rate, P denotes the receiving power, both n and m are positive integers, the number of summation items is 2m, and k denotes the relative delay between the two multiplicative receiving power values, k=0, 1, 2 . . . ,

wherein the voltage controlled oscillator is further connected to the analog-digital converter and configured to drive the analog-digital converter for sampling, the phase detector is further connected to the dispersion compensator and configured to detect a phase difference, and the clock recovery apparatus being configured to perform clock recovery.

6. A dual-polarization digital coherent receiver, comprising:

a coherent detector configured to convert a received optical signal into an electrical signal;

an analog-digital converter connected to the coherent detector and configured to perform analog-digital conversion to an I-th component and Q-th component of the received signal at x polarization state and the I-th component and Q-th component of the received signal at y polarization state outputted by the coherent detector;

a dispersion compensator connected to the analog-digital converter and configured to perform dispersion compensation respectively to the received signals at x polarization state and y polarization state outputted by the analog-digital converter;

a data recovery apparatus connected to the dispersion compensator and configured to perform data recovery to the received signals at x polarization state and y polarization state to which dispersion compensation has been performed by the dispersion compensator; and

a clock recovery apparatus comprising a voltage controlled oscillator and a phase detector, the voltage controlled oscillator is configured to drive an analog-digital converter for sampling, the phase detector is connected to the voltage controlled oscillator and configured to detect a phase difference,

wherein the phase detector comprises a calculation unit which is configured to calculate a phase difference according to a product of receiving power at different moments, so as to perform clock recovery by using the phase difference, wherein the receiving power is that obtained in sampling input signals at a predefined sampling rate, the predefined sampling rate being 2 times of a symbol rate, wherein the calculation unit uses the formula below to calculate the phase difference:

s 2n =Σ i=0 2m−1 (−1) i P 2n−i P 2n−i−k ;

where, s denotes the output of the phase detector, subscript 2n denotes a serial number of a sampling point, the predefined sampling rate is 2 times of a symbol rate, P denotes the receiving power, both n and m are positive integers, the number of summation items is 2m, and k denotes the relative delay between the two multiplicative receiving power values, k=0, 1, 2 . . . ,

wherein the voltage controlled oscillator is further connected to the analog-digital converter, the phase detector is further connected to the dispersion compensator, and the clock recovery apparatus being configured to perform clock recovery.

7. A clock recovery apparatus, comprising:

a resampler configured to resample a received signal; and

a phase detector connected to the resampler and configured to detect a phase difference,

wherein the phase detector comprises a calculation unit which is configured to calculate a phase difference according to a product of receiving power at different moments, so as to perform clock recovery by using the phase difference, wherein the receiving power is that obtained in sampling input signals at a predefined sampling rate, the predefined sampling rate being 2 times of a symbol rate, wherein the calculation unit uses the formula below to calculate the phase difference:

s 2n =Σ i=0 2m−1 (−1) i P 2n−i P 2n−i−k ;

where, s denotes the output of the phase detector, subscript 2n denotes a serial number of a sampling point, the predefined sampling rate is 2 times of a symbol rate, P denotes the receiving power, both n and m are positive integers, the number of summation items is 2m, and k denotes the relative delay between the two multiplicative receiving power values, k=0, 1, 2 . . . .

8. A single-polarization digital coherent receiver, comprising:

a coherent detector configured to convert a received optical signal into an electrical signal;

an analog-digital converter connected to the coherent detector and configured to perform analog-digital conversion to an I-th component and Q-th component of the received signal outputted by the coherent detector;

an oscillator connected to the analog-digital converter and configured to drive the analog-digital converter for sampling;

a clock recovery apparatus connected to the analog-digital converter and configured to perform clock recovery;

a dispersion compensator connected to the clock recovery apparatus and configured to perform dispersion compensation to the received signal outputted by the analog-digital converter; and

a data recovery apparatus connected to the dispersion compensator and configured to perform data recovery to the received signal to which dispersion compensation has been performed by the dispersion compensator;

wherein the clock recovery apparatus comprises a resampler and a phase detector, the resampler is configured to resample a received signal, the phase detector is connected to the resampler and configured to detect a phase difference,

wherein the phase detector comprises a calculation unit which is configured to calculate a phase difference according to a product of receiving power at different moments, so as to perform clock recovery by using the phase difference, wherein the receiving power is that obtained in sampling input signals at a predefined sampling rate, the predefined sampling rate being 2 times of a symbol rate, wherein the calculation unit uses the formula below to calculate the phase difference:

s 2n =Σ i=0 2m−1 (−1) i P 2n−i P 2n−i−k ;

where, s denotes the output of the phase detector, subscript 2n denotes a serial number of a sampling point, the predefined sampling rate is 2 times of a symbol rate, P denotes the receiving power, both n and m are positive integers, the number of summation items is 2m, and k denotes the relative delay between the two multiplicative receiving power values, k=0, 1, 2 . . . ,

wherein the resampler is disposed between the analog-digital converter and the dispersion compensator and configured to resample a received signal, and the phase detector is further connected to the dispersion compensator and configured to detect a phase difference.

9. A dual-polarization digital coherent receiver, comprising:

a coherent detector configured to convert a received optical signal into an electrical signal;

an analog-digital converter connected to the coherent detector and configured to perform analog-digital conversion to an I-th component and Q-th component of the received signal at x polarization state and the I-th component and Q-th component of the received signal at y polarization state outputted by the coherent detector;

an oscillator connected to the analog-digital converter and configured to drive the analog-digital converter for sampling;

a clock recovery apparatus connected to the analog-digital converter and configured to perform clock recovery;

a dispersion compensator connected to the clock recovery apparatus and configured to perform dispersion compensation respectively to the received signals at x polarization state and y polarization state outputted by the analog-digital converter; and

a data recovery apparatus connected to the dispersion compensator and configured to perform data recovery to the received signals at x polarization state and y polarization state to which dispersion compensation has been performed by the dispersion compensator;

wherein the clock recovery apparatus comprises a resampler and a phase detector, the resampler is configured to resample a received signal, the phase detector is connected to the resampler and configured to detect a phase difference,

wherein the phase detector comprises a calculation unit which is configured to calculate a phase difference according to a product of receiving power at different moments, so as to perform clock recovery by using the phase difference, wherein the receiving power is that obtained in sampling input signals at a predefined sampling rate, the predefined sampling rate being 2 times of a symbol rate, wherein the calculation unit uses the formula below to calculate the phase difference:

s 2n =Σ i=0 2m−1 (−1) i P 2n−i P 2n−i−k ;

where, s denotes the output of the phase detector, subscript 2n denotes a serial number of a sampling point, the predefined sampling rate is 2 times of a symbol rate, P denotes the receiving power, both n and m are positive integers, the number of summation items is 2m, and k denotes the relative delay between the two multiplicative receiving power values, k=0, 1, 2 . . . ,

wherein the resampler is disposed between the analog-digital converter and the dispersion compensator and configured to resample a received signal, and the phase detector is further connected to the dispersion compensator and configured to detect a phase difference.