IP Library Granted Patent US 9,166,540
Granted Patent B2
US 9,166,540 · App. 14/049,588 · Granted Oct 20, 2015

Gain invariant impedance feedback amplifier

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Quick Facts
Patent No.
US 9,166,540
App. No.
14/049,588
Granted
Oct 20, 2015
Kind
B2
Abstract

A system includes a weighting element, a transconductance circuit, a feedback loop, and an auxiliary loop. In some implementations, the transconductance circuit may accept an input and provide a first portion of an output for amplification at a variable amplification level to generate an amplifier output. The feedback loop may provide a portion of the amplifier output as a first feedback to the input. The first feedback may be associated with an impedance that may vary with the amplification level. The auxiliary loop may provide a second feedback to the input to reduce the dependence of the impedance on the amplification level.

Claims (49)

1. A system, comprising:

a transconductance circuit comprising an input and a first output;

a weighting element coupled to the first output, the weighting element comprising:

a first path configured to produce an amplifier output responsive to the first output; and

a second path configured to split off an auxiliary portion of the first output;

a feedback loop comprising a variable impedance configured have a dependence on an amplification level of the amplifier output, the feedback loop configured to provide a first portion of the amplifier output as a first feedback to the input responsive to the variable impedance; and

an auxiliary loop configured to:

accept the auxiliary portion of the first output; and

reduce the dependence of the variable impedance responsive to the amplification level by providing, to the input, a second feedback dependent on the amplification level and responsive to the auxiliary portion.

2. The system of claim 1 , where the weighting element further comprises a third path configured to split off a second portion of the first output.

3. The system of claim 2 , where the weighting element comprises a first transistor for the first path, a second transistor for the second path, and a third transistor for the third path.

4. The system of claim 3 , where the first, second and third transistors comprise finger elements.

5. The system of claim 4 , where the first transistor comprises a first number of finger elements, the second transistor comprises a second number of finger elements, the third transistor comprises a third number of finger elements; and

where a difference of the first and third numbers is equal to the second number.

6. The system of claim 4 , where the finger elements comprise switchable finger elements;

where the system further comprises switches for the switchable finger elements to adjust the variable impedance via adjustment of a ratio between the amplifier output and auxiliary portion; and

where the variable impedance arises from opposing responsivities of the variable impedance and the amplification level dependent feedback.

7. The system of claim 3 , where the amplifier output is generated by a first current through the first transistor; and

where a second current through the third transistor is accepted by a power supply.

8. The system of claim 3 , where the first transistor is configured to be controlled by a first control voltage, and the second and third transistors are configured to be controlled by a second control voltage.

9. The system of claim 2 , where the amplifier output is configured to increase as the amplification level increases and the second portion and auxiliary portion are configured to decrease as the amplification level increases.

10. The system of claim 1 , where the feedback loop is configured to provide the first feedback across a resistive element; and

the first feedback comprises negative feedback.

11. A method, comprising:

amplifying a first portion of a first output to generate an amplifier output, the amplifier output related to an input by an amplification level;

providing, via a feedback loop, a portion of the amplifier output as a first feedback to the input;

varying a first magnitude of the amplifier output in proportion to the amplification level; providing, via an auxiliary loop, an auxiliary portion of the first output as a second feedback to the input; and

varying a second magnitude of the second feedback inversely to the amplification level to reduce a dependence of a variable impedance responsive to the amplification level.

12. The method of claim 11 , where the varying the second magnitude comprises maintaining a sum of the first and second magnitudes at a value independent of the amplification level.

13. The method of claim 11 , further comprising:

providing a second portion of the first output to a power supply.

14. The method of claim 11 , where the providing the portion of the amplifier output comprises providing the portion of the amplifier output across a resistive element.

15. The method of claim 11 , further comprising varying the amplification level such that a time-averaged magnitude of the amplifier output is constant.

16. The method of claim 11 , further comprising varying the amplification level over a continuous range.

17. A device, comprising:

a transconductance circuit comprising:

an input at a first terminal of a transconductance transistor,

a resistor situated between a ground and a second terminal of the transconductance transistor; and

a first output at a third terminal of the transconductance transistor, a current between the ground and first output configured to be controlled via the input;

a weighting element comprising:

a first transistor, over which a first portion of the first output traverses, the first transistor comprising a first number of finger elements, the first transistor configured to amplify the first portion to generate an amplifier output, the input being related to the amplifier output by an amplification level;

a second transistor over which a second portion of the first output traverses, the second transistor comprising a second number of finger elements, a difference between the first and second numbers being equal to a third number, a relationship between a first portion magnitude and a second portion magnitude being dependent on the amplification level;

a third transistor over which an auxiliary portion of the first output traverses, the third transistor comprising the third number of finger elements; and

a feedback loop configured to provide a portion of the amplifier output across a resistor to serve as a first feedback to the input; and

an auxiliary loop comprising:

a path configured to provide a second feedback to the input responsive to the auxiliary portion, the third transistor configured to vary a second feedback magnitude inversely to the amplification level.

18. The device of claim 17 , where the amplification level comprises a continuously variable amplification level.

19. The device of claim 18 , where the device comprises an amplifier device in an automatic gain control circuit.

20. The device of claim 19 , where the amplifier output comprises a constant time-averaged level.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2013
From: CUSMAI, GIUSEPPE; PERIASAMY, VIJAYARAMALINGAM; CHEN, XI; GOMEZ, RAMON ALEJANDRO
To: BROADCOM CORPORATION
Reel/Frame 031374/0109 →