Vertical type semiconductor memory apparatus and fabrication method thereof
View Patent ↗Semiconductor memory apparatus and a method of fabricating the same are provided. The semiconductor memory apparatus includes a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the a cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height corresponding to the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part.
1. A semiconductor memory apparatus, comprising:
a semiconductor substrate in which a cell area and a peripheral area are defined by device isolation layer;
a plurality of pillars formed in the cell area of the semiconductor substrate to a first depth;
a stepped part formed in the peripheral area to a height substantially the same as the first depth;
a recessed part formed in the stepped part to a second depth; and
a core switching device formed in the recessed part.
2. The semiconductor memory apparatus of claim 1 , wherein the first depth is the same as or different from the second depth.
3. The semiconductor memory apparatus of claim 1 , further comprising:
a cell gate insulating layer foamed to surround each of the pillars to a predetermined height; and
a gate conductive layer formed to surround the cell gate insulating layer.
4. The semiconductor memory apparatus of claim 3 , further comprising:
a lower electrode formed on each of the pillars; and
a data storage unit formed on the lower electrode.
5. The semiconductor memory apparatus of claim 4 , wherein the data storage unit includes a material of which a resistance value is changed according to a voltage or a current supplied thereto.
6. The semiconductor memory apparatus of claim 1 , wherein the data storage unit includes one selected from the group including a phase-change material, a transition metal oxide, perovskite, and a polymer.
7. The semiconductor memory apparatus of claim 1 , wherein the core switching device includes a single-layered gate conductive layer or a multi-layered gate conductive layer.
8. A semiconductor memory apparatus, comprising:
a semiconductor substrate in which a cell area and a peripheral area are defined by device isolation layer;
a plurality of pillars having a first depth formed in the cell area of the semiconductor substrate;
a recessed part having a second depth formed in the peripheral area of the semiconductor substrate; and
a core switching device formed in the recessed part.
9. The semiconductor memory apparatus of claim 8 , further comprising a stepped part having a height substantially the same as the first depth, formed in the peripheral area, wherein the recessed part is formed in the stepped part.
10. The semiconductor memory apparatus of claim 1 , wherein the first depth is the same as or different from the second depth.