Digital-to-analog converter and a method of operating a digital-to-analog converter

1. A digital-to-analog converter (DAC) comprising:

a first section including a converter network of a first type having a first plurality of current flow paths forming binary weighted values in the DAC; and

a second section including a second converter network of the first type, connected to the first section, and having a second plurality of current flow paths;

wherein the first and second sections are joined together by a shared connection to an output node of the DAC,

wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and

wherein weights of one or more of the second plurality of current flow paths are substantially equal to weights of one or more of the first plurality of current flow paths to provide redundancy in the DAC.

2. A DAC as claimed in claim 1 , wherein the first type is a R-2R ladder network.

3. A DAC as claimed in claim 1 , wherein the second plurality of current flow paths form binary weighted values in the DAC.

4. A DAC as claimed in claim 3 , wherein the second section further comprises a fourth plurality of current flow paths forming binary weighted values in the DAC.

5. A DAC as claimed in claim 1 , wherein the first node is connected to a first reference voltage and the second node is connected to a second reference voltage.

6. A DAC as claimed in claim 1 , wherein the second section further comprises a third plurality of current flow paths forming equally weighted values in the DAC.

7. A DAC as claimed in claim 6 , further comprising a controller operable to drive switches for controlling each of the current flow paths of the DAC so as to delay the transition of one or more of the third plurality of current flow paths until one or more lower weighted current flow paths of the first section are switched into connection with the first node.

8. A DAC as claimed in claim 7 , wherein the controller drives at least some of the switches of the DAC in response to an error value resulting at least partially from errors in values of components in the DAC, or due to changes in the values that occur in use.

9. A DAC as claimed in claim 8 , wherein the error value results from errors in values of components of the DAC having a significant contribution to the output voltage of the DAC.

10. A DAC as claimed in claim 7 , further comprising memory for storing one or more of the component values or error values of components in the DAC.

11. A DAC as claimed in claim 7 , wherein a first current flow path of the first plurality of current flow paths and a second current flow path of the second plurality of current flow paths have a combined output voltage contribution of N volts, and wherein the controller is operable to drive the switches of the DAC such that transition of the first and second current flow paths from the first reference voltage to the second reference voltage coincides with a transition of a third current flow path of the DAC having an output voltage contribution of N volts from the second reference voltage to the first reference voltage.

12. A method of driving a digital-to-analog converter (DAC) comprising:

receiving an input DAC code;

deriving an output DAC code which differs from the input code;

driving selective switches of a first section including a converter network of a first type having a first plurality of current flow paths forming binary weighted values in the DAC based on the output DAC code; and

driving selective switches a second section connected to the first section and including a second converter network of the first type having a second plurality of current flow paths based on the output DAC code,

wherein weights of one or more of the second plurality of current flow paths are substantially equal to weights of one or more of the first plurality of current flow paths to provide redundancy in the DAC.

13. A method as claimed in claim 12 , wherein the output DAC code is derived such that transition of a weighted current flow path having a first weight only takes place when one or more weighted current flow paths of the first binary weighted section and having weights less than the first weight are switched into connection with the second node.

14. A method as claimed in claim 13 , wherein the value of error results from errors in values of current flow paths of the DAC having a contribution above a first threshold to the output voltage of the DAC.

15. A method as claimed in claim 12 , wherein the step of deriving the output DAC code comprises:

calculating an error value based on one or more errors in values of components in the DAC; and

adjusting the output DAC code based at least partially on the calculated error value.

16. A method as claimed in claim 12 , wherein the output DAC code is derived such that a first current flow path of the first plurality of current flow paths and a second current flow path of the second plurality of current flow paths having a combined output voltage contribution of N volts are switched from the first node to the second node at the same time as a third current flow path of the DAC having an output voltage contribution of N volts is switched from the second node to the first node.

17. An integrated circuit, comprising:

a digital-to-analog converter (DAC) comprising:

a first section including a converter network of a first type having a first plurality of current flow paths forming binary weighted values in the DAC; and

a second section connected to the first section and including a second converter network of the first type having a second plurality of current flow paths;

wherein the first and second sections are joined together by a shared connection to an output node of the DAC,

wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and

wherein weights of one or more of the second plurality of current flow paths are substantially equal to weights of one or more of the first plurality of current flow paths to provide redundancy in the DAC.

18. The integrated circuit of claim 17 , wherein the first type is a R-2R ladder network.

19. A digital-to-analog converter (DAC) comprising:

a first section including a converter network of a first type having a first plurality of current flow paths forming binary weighted values in the DAC; and

a second section including a second converter network of the first type, connected to the first section at an output node of the DAC, the second section having a second plurality of current flow paths forming binary weighted values in the DAC and a third plurality of current flow paths forming substantially equally weighted values in the DAC,

wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are substantially equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.

20. The DAC of claim 19 , wherein the first type is a R-2R ladder network.