Semiconductor package
View Patent ↗A semiconductor package is provided. The semiconductor package includes a substrate, a first pad, a second, a first conductive element, a surface mount device, a first bonding wire and a molding compound layer. The first pad, the second pad, and the first conductive element are formed on the substrate. The surface mount device is mounted on the first pad and the second pad. The first bonding wire electrically connects the first conductive element and the first pad. The molding compound layer encapsulates the substrate, the first pad, the second pad, the first conductive element, the bonding wire and the surface mount device.
1. A semiconductor package, comprising:
a substrate;
a first pad formed on the substrate;
a second pad formed on the substrate;
a first conductive element formed on the substrate;
a surface mount device mounted on the first pad and the second pad;
a first bonding wire electrically connecting a first bonding area of the first conductive element and a second bonding area of the first pad;
a second conductive element formed on the substrate, and formed between the first pad and the first conductive element;
a solder resistance layer, covering a portion of the first bonding area and a portion of the second bonding area;
a molding compound layer encapsulating the substrate, the first pad, the second pad, the first conductive element, the second conductive element, the bonding wire and the surface mount device.
2. The semiconductor package according to claim 1 , further comprising:
a via-plug formed in the substrate and connecting to the second pad.
3. The semiconductor package according to claim 2 , wherein the via-plug is covered by a solder resistance layer and located in a space between the first pad and the second pad.
4. The semiconductor package according to claim 1 , further comprising:
a third conductive element formed on the substrate; and
a second bonding wire electrically connecting the third conductive element and the second pad.
5. The semiconductor package according to claim 4 , further comprising:
a fourth conductive element formed on the substrate, and formed between the second pad and the third conductive element;
wherein the second bonding wire lies across the fourth conductive element.
6. The semiconductor package according to claim 4 , wherein the third conductive element is a power trace, a power ring, a power plane, or a power finger.
7. The semiconductor package according to claim 1 , wherein the first conductive element is a power trace, a power ring, a power plane, or a power finger.
8. A semiconductor package, comprising:
a substrate;
a first pad formed on the substrate;
a second pad formed on the substrate;
a via-plug formed in the substrate, covered by a solder resistance layer, located in a space between the first pad and the second pad, and electrically connected to the second pad;
a surface mount device mounted on the first pad and the second pad; and
a molding compound layer encapsulating the substrate, the first pad, the second pad, the solder resistance layer and the surface mount device.
9. The semiconductor package according to claim 8 , further comprising a first conductive element formed on the substrate; and
a first bonding wire electrically connecting the first conductive element and the first pad.
10. The semiconductor package according to claim 9 , further comprising a second conductive element formed on the substrate, and formed between the first pad and the first conductive element;
wherein the first bonding wire lies across the second conductive element.
11. The semiconductor package according to claim 9 , wherein the first conductive element is a power trace, a power ring, a power plane, or a power finger.
12. The semiconductor package according to claim 8 , further comprising:
a third conductive element formed on the substrate; and
a second bonding wire electrically connecting the third conductive element and the second pad.
13. The semiconductor package according to claim 12 , further comprising:
a fourth conductive element formed on the substrate, and formed between the second pad and the third conductive element.
14. The semiconductor package according to claim 12 , wherein the third conductive element is a power trace, a power ring, a power plane, or a power finger.