Spacer formation with straight sidewall
View Patent ↗Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion substantially perpendicular to the substrate. The perimeter further includes a discontinuity at an interface of the top curved portion with the vertical portion. Further, disclosed herein are methods associated with the fabrication of the aforementioned semiconductor device.
1. A method of fabricating a semiconductor device, comprising:
disposing a gate structure on a substrate, the gate structure comprising:
a gate, a first dielectric disposed beneath the gate, and a second dielectric at least on sidewalls of the gate and over the gate;
disposing a first layer of material over the second dielectric;
disposing a second layer of material over the first layer of material;
etching the second layer of material such that portions of the second layer of material remain on sidewalls of the first layer of material;
etching the first layer of material with an etchant having substantially higher selectivity to the first layer of material than to the second layer of material; and
etching the portions of the second layer of material remaining on the sidewalls of the first layer of material.
2. The method of claim 1 , wherein disposing the first layer of material comprises disposing polycrystalline silicon.
3. The method of claim 1 , wherein disposing the second layer of material comprises disposing silicon nitride or silicon dioxide.
4. The method of claim 1 , wherein disposing the second layer of material comprises disposing a film of the second layer of material that is substantially thinner than the first layer of material.
5. The method of claim 1 , wherein disposing the second dielectric comprises disposing silicon nitride or silicon dioxide wherein the second dielectric comprises at least one type of dielectric material.
6. The method of claim 1 , wherein disposing the gate structure, comprises disposing the first dielectric by sequentially depositing oxide, nitride, and oxide (ONO) layers.
7. A method of fabricating a semiconductor device, comprising:
forming a first dielectric layer on a substrate;
forming a first gate layer over the first dielectric layer;
patterning the first gate layer and the first dielectric layer to form a first gate stack;
forming a second dielectric layer over at least the first gate stack and the substrate;
forming a first layer of material over the second dielectric layer;
forming a second layer of material over the first layer of material;
removing a portion of the second layer of material wherein an unremoved portion of the second layer of material remains on sidewalls of the first layer of material;
etching the first layer of material with an etchant having substantially higher selectivity to the first layer of material than to the second layer of material;
etching the unremoved portion of the second layer of material remaining on the sidewalls of the first layer of material.
8. The method of claim 7 , wherein the first layer of material includes polycrystalline silicon.
9. The method of claim 7 , wherein the second layer of material includes silicon nitride or silicon dioxide.
10. The method of claim 7 , wherein forming the second layer of material comprises disposing a film of the second layer of material that is substantially thinner than the first layer of material.
11. The method of claim 7 , wherein the second dielectric layer includes silicon nitride or silicon dioxide, and wherein the second dielectric layer includes at least one type of dielectric material.
12. The method of claim 7 , wherein forming the first dielectric layer comprises sequentially depositing oxide, nitride, and oxide (ONO) layers.
13. The method of claim 7 , wherein forming the second dielectric layer, forming the first layer of material, and forming a second layer of material includes utilizing a conformal deposition process.
14. The method of 7 , wherein etching the unremoved portion of the second layer of material causes the first layer of material to be a spacer of the semiconductor device, wherein the spacer includes a cross-section comprising a perimeter that includes a top curved portion and a vertical portion substantially perpendicular to the substrate, and the perimeter including a discontinuity at an interface of the top curved portion with the vertical portion.
15. A method of fabricating a semiconductor device, comprising:
disposing a gate structure on a substrate, the gate structure comprising:
a gate, a first dielectric disposed beneath the gate, and a second dielectric at least on sidewalls of the gate and over the gate;
disposing a first layer of material over the second dielectric, wherein the first layer of material includes polycrystalline silicon;
disposing a second layer of material over the first layer of material;
etching the second layer of material such that portions of the second layer of material remain on sidewalls of the first layer of material; and
etching the first layer of material with an etchant having substantially higher selectivity to the first layer of material than to the second layer of material.