Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts
View Patent ↗Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, a punch out bit field, or a cryptographic command. The commands may be transmitted using a broadcast scheme or a split transaction scheme. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level.
1. A memory module, comprising:
a plurality of memory cells; and
a plurality of signal lines for communicating with a processing device, the memory module configured such that following initial reception of a command and upon encountering a busy condition while processing the command, the memory module clamps a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time to report to the processing device an occurrence of the busy condition;
wherein the memory module is configured to concurrently 1) receive a first binary input signal on the first signal line and 2) report to the processing device the occurrence of the busy condition by clamping the voltage of the first binary input signal to be no more than the intermediate voltage such that the voltage-clamped first binary input signal is in the binary one state when the first binary input signal is at the intermediate voltage and in the binary zero state when the first binary input signal is at a voltage level corresponding to the binary zero state, the first binary input signal being a clock input signal for use by the memory module for executing the command.
2. The memory module of claim 1 , further comprising at least one resistor coupled between the first signal line and a ground potential, the memory module causing current to pass through the at least one resistor for clamping the voltage on the first signal line to be no more than the intermediate voltage.
3. The memory module of claim 2 , wherein the intermediate voltage is based at least in part upon a resistance of the at least one resistor.
4. The memory module of claim 1 , further comprising at least one diode coupled between the first signal line and a ground potential, the memory module causing current to pass through the at least one diode for clamping the voltage on the first signal line to be no more than the intermediate voltage.
5. The memory module of claim 1 , further comprising at least one electrical component coupled between the first signal line and a ground potential, the memory module causing current to pass through the at least one electrical component for clamping the voltage on the first signal line to be no more than the intermediate voltage.
6. The memory module of claim 1 , wherein the plurality of signal lines includes a second signal line, and wherein upon encountering an error condition when processing the command, the memory module clamps a voltage on the second signal line to be no more than a second intermediate voltage between the voltages corresponding to the logic zero state and the voltages corresponding to the logic one state for a second period of time to report the error condition to the processing device.
7. The memory module of claim 6 , wherein the second intermediate voltage is substantially the same as the clamped intermediate voltage on the first signal line.
8. The memory module of claim 6 , wherein the memory module concurrently 1) receives on the second signal line a second binary input signal and 2) reports to the processing device the error condition by clamping the voltage of the second binary input signal to be no more than the second intermediate voltage, the second binary input signal comprising an address-data signal.
9. The memory module of claim 6 , further comprising at least one resistor coupled between the second signal line and a ground potential, the memory module causing current to pass through the at least one resistor for clamping the voltage on the second signal line to be no more than the second intermediate voltage.
10. The memory module of claim 6 , further comprising at least one diode coupled between the second signal line and a ground potential, the memory module causing current to pass through the at least one diode for clamping the voltage on the second signal line to be no more than the second intermediate voltage.
11. The memory module of claim 6 , further comprising at least one electrical component coupled between the second signal line and a ground potential, the memory module causing current to pass through the at least one electrical component for clamping the voltage on the second signal line to be no more than the second intermediate voltage.
12. The memory module of claim 1 , wherein the memory module includes a counter and the memory module executes the command at least in part by incrementing the counter.
13. The memory module of claim 12 , wherein the command includes a punch out bit field command which, when executed by the memory module, causes the memory module to punch out at least one specified bit in the memory module indicative of usage of toner or ink.
14. The memory module of claim 1 , wherein the command includes a punch out bit field command which, when executed by the memory module, causes the memory module to punch out at least one specified bit in the memory module indicative of usage of toner or ink.
15. A memory module, comprising:
memory cells for storing information therein; and
a plurality of signal lines for communicating with a processing device, the memory module configured such that during processing of a command received on at least one of the plurality of signal lines, a voltage on a first signal line of the plurality of signal lines is clamped for a period of time by the memory module to be no more than an intermediate voltage greater than voltages corresponding to a binary zero value and less than voltages corresponding to a binary one value, the voltage clamping for communicating by the memory module to the processing device an occurrence of one of a busy condition and an error condition;
wherein the memory module is configured to concurrently 1) receive a first binary input signal on the first signal line and 2) clamp the voltage of the first binary input signal to be no more than the intermediate voltage such that the voltage-clamped first binary input signal being at the intermediate voltage instead of one of the voltages corresponding to the binary one value communicates the occurrence of the one of the busy condition and the error condition by the memory module.
16. The memory module of claim 15 , wherein the first binary input signal is one of a clock input signal and an address-data input signal, the first binary input signal being used by the memory module to execute the command.
17. The memory module of claim 15 , further comprising at least one electrical component coupled between the first signal line and a ground potential such that the memory module passes current through the at least one electrical component for clamping the voltage on the first signal line to be no more than the intermediate voltage.
18. The memory module of claim 17 , wherein the intermediate voltage is based at least in part upon a resistance corresponding to the at least one electrical component.
19. The memory module of claim 15 , further comprising at least one diode coupled between the first signal line and a ground potential such that the memory module passes current through the at least one diode for clamping the voltage on the first signal line to be no more than the intermediate voltage.
20. The memory module of claim 15 , wherein the plurality of signal lines includes a second signal line, and wherein the memory module is configured such that during processing of a received second command and upon encountering the other one of the busy condition and the error condition, a voltage on the second signal line is clamped for a second period of time by the memory module to be no more than a second intermediate voltage greater than the voltages corresponding to the binary zero value and less than the voltages corresponding to the binary one value, for indicating the other one of the busy condition and the error condition.
21. The memory module of claim 20 , wherein the second intermediate voltage is substantially the same as the clamped intermediate voltage on the first signal line.
22. The memory module of claim 15 , wherein the command includes a punch out bit field command which, when executed by the memory module, causes the memory module to punch out at least one specified bit in the memory module indicative of usage of toner or ink.
23. The memory module of claim 22 , wherein the memory module includes a counter and the memory module executes the command at least in part by incrementing the counter.
24. A memory module, comprising:
a plurality of memory cells; and
a plurality of signal lines for communicating with a processing device, the memory module configured such that in response to encountering a busy condition while processing a command, the memory module clamps a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time to communicate to the processing device an occurrence of the busy condition;
wherein the memory module is configured to receive a first binary input signal on the first signal line during the period of time the memory module clamps the voltage on the first signal line to be no more than the intermediate voltage such that the voltage-clamped first binary input signal being at the intermediate voltage instead of one of the voltage levels corresponding to the binary one state communicates by the memory module to the processing device the occurrence of the busy condition, the first binary input signal comprising an input clock signal.