IP Library Granted Patent US 9,454,421
Granted Patent B2
US 9,454,421 · App. 14/054,265 · Granted Sep 27, 2016

Method for providing read data flow control or error reporting using a read data strobe

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Quick Facts
Patent No.
US 9,454,421
App. No.
14/054,265
Granted
Sep 27, 2016
Kind
B2
Abstract

Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture. If the read data strobe signal is not received before expiration of a predetermined maximum latency time, the peripheral controller is indicating a read data error back to the host.

Claims (28)

1. A method comprising:

transmitting address information and a read request from a host device to a peripheral device;

counting clock pulses until a read data strobe signal is received from the peripheral device;

using the read data strobe signal as a time reference to indicate when valid data is available for capture;

capturing valid data at a host interface using the time reference; and

in response to a number of the clock pulses being greater than a predetermined maximum latency from among a plurality of predetermined maximum latencies:

reporting a data error to the host interface; and

preventing capture of read data at the host interface.

2. The method of claim 1 , further comprising:

receiving the read data strobe signal before a first predetermined maximum time of receipt; and

controlling latency of the read request that initiates return of the valid data from the peripheral device to the host interface.

3. The method of claim 2 , further comprising:

receiving the read data strobe signal before a second predetermined maximum time of receipt; and

controlling latency between data transfers to provide control of a rate of transfer in a series of data transfers from the peripheral device to the host interface.

4. The method of claim 3 , wherein a read operation comprises one of a single read, a continuous read, or a wrapped read.

5. The method of claim 1 , further comprising:

when the read request is for a return of multiple data elements, receiving the read data strobe signal for each data element transfer from the peripheral device to the host interface.

6. The method of claim 1 , wherein the predetermined maximum latency comprises a number of pulses generated by a clock, the clock communicating from the host interface to the peripheral device.

7. The method of claim 6 , wherein the data error occurs at one of an initial data page access or a boundary crossing between data pages of the peripheral device.

8. The method of claim 1 , wherein the predetermined maximum latency is set by software in the host device at least before initiating a data read operation.

9. The method of claim 1 , further comprising:

receiving the valid data at the host interface when a number of the clock pulses is less than or equal to the predetermined maximum latency; and

receiving timing information at the host device that aids in the capture of the valid data.

10. The method of claim 1 , wherein preventing capture of the read data at the host interface further comprises receiving, at the host device, data error information about the data error.

11. The method of claim 1 , further comprising:

receiving the valid data before an expected time of receipt or after a delay at the host interface; and

receiving variable timing information at the host device.

12. The method of claim 1 , wherein a delay or a time period before an expected time of receipt comprises the difference between the number of clock pulses until the read data strobe signal is received and a number of pulses comprising the predetermined maximum latency as set by the clock.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2015
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 035884/0410 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2013
From: MCCLAIN, MARK ALAN; HASAN, QAMRUL; ZITLAW, CLIFFORD ALAN
To: SPANSION LLC
Reel/Frame 031409/0172 →