Memory program upon system failure
View Patent ↗A system and method for programming a memory device with debug data upon a system failure is disclosed herein. For example, the system can include a timer device, a buffer, a register, and a memory device. The buffer can be configured to receive debug data. The register can be configured to receive memory address information. Also, the memory device can be configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero. Further, the system can include a processing unit configured to provide the timer value to the timer device and the memory address information to the register.
1. A system comprising:
a timer device integrated on a host device;
a buffer, integrated on an another device, configured to receive debug data representative of one or more probed nodes in the system;
a register, integrated on the another device, configured to receive memory address information; and
a memory device, integrated on the another device, configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero, wherein the buffer is configured to transfer the debug data to the memory device in response to a system failure program command issued on a dedicated line.
2. The system of claim 1 , further comprising:
a processing unit configured to provide the timer value to the timer device and the memory address information to the register.
3. The system of claim 1 , wherein the timer device comprises a watchdog timer.
4. The system of claim 1 , wherein the debug data stored in the buffer is updated if the timer value of the timer device has not reached zero.
5. The system of claim 1 , wherein the buffer comprises a volatile memory device and the memory device comprises a non-volatile memory device.
6. The system of claim 1 , wherein the host device is in communication with the memory device.
7. The system of claim 6 , wherein the buffer is configured to transfer the debug data to the memory device via a data bus coupling the host device to the memory device.
8. The system of claim 1 , wherein the memory device is configured to receive the debug data from the buffer.
9. The system of claim 1 , wherein the timer device is configured to transmit the system failure program command on the dedicated line when the timer value reaches zero.
10. The system of claim 1 , wherein the dedicated line comprises a connection between a dedicated pin on the host device and a corresponding dedicated pin on the another device.
11. The system of claim 1 , wherein the dedicated line transfers the debug data between a host device and the memory device, and wherein the host device comprises a processing unit.
12. A method comprising:
receiving debug data in a buffer;
receiving memory address information in a register; and
storing, in a memory device, the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of a timer device reaches zero, wherein the debug data is representative of one or more probed nodes in a system comprising the buffer, register, memory device, and timer device, wherein the timer device is integrated on a host device, wherein the buffer, the register, and the memory device are integrated on another device, and wherein the storing comprises receiving, at the memory device, the debug data from the buffer; and
transmitting the debug data in the buffer to the memory device in response to a system failure program command issued on a dedicated line.
13. The method of claim 12 , further comprising:
updating the debug data in the buffer when the timer value of the timer device has not reached zero.
14. The method of claim 12 , wherein the storing comprises the receiving, at the memory device, the debug data over a data bus coupling the host device to the memory device.