Flexible allocation of I/O channels of a hardware component

1. A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA (Field Programmable Gate Array), and a plurality of I/O (Input/Output) channels, the hardware component being connectable to a computer system, the I/O channels being connectable to the FPGA, and the FPGA being connectable to the processor via a communications interface, the method comprising:

selecting a first subset of the I/O channels for operation by the FPGA;

generating a first application program to be executed by the FPGA;

selecting a second subset of the I/O channels for operation by the processor based on the selected first subset of the I/O channels;

generating a second application program to be executed by the processor;

generating an application model for the hardware component,

embedding the first application program in the second application program,

storing the second application program with the embedded first application program in a memory assigned to the processor for execution by the processor, and

executing the first application program and the second application program,

wherein the step of generating the first application program comprises model-based automatic generation of code based on the application model for the hardware component,

wherein the step of generating a first application program comprises the generation of code for connecting the second subset of the I/O channels to the communications interface,

wherein the step of generating code for connecting the second subset of the I/O channels to the communications interface comprises the automatic generation of code for connecting I/O channels that are part of the second subset of I/O channels, and

based on the executed first application program and second application program, connecting the hardware component of the computer system, wherein the hardware component includes the I/O channels, the FPGA, and the processor, with the I/O channels connecting to the FPGA, and the FPGA connecting to the processor, via the communication interface.

2. The method according to claim 1 , wherein the step of generating code for connecting the second subset of the I/O channels to the communications interface comprises the generation of code for executing a signal processing between at least one of the I/O channels of the second subset and the communications interface.

3. The method according to claim 1 , wherein the step of generating the first application program comprises providing identification information of I/O channels of the first subset.

4. The method according to claim 1 , wherein the step of generating the first application program comprises receiving identification information of the I/O channels of the second subset.

5. The method according to claim 1 , further comprising generating an application model, wherein the step of generating the second application program comprises model-based automatic generation of code.

6. The method according to claim 5 , wherein the step of generating the second application program comprises providing identification information of the I/O channels of the second subset.

7. The method according to claim 5 , wherein the step of generating the second application program comprises receiving identification information of the I/O channels of the first subset.

8. A method for operating a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels, wherein the I/O channels are connectable to the FPGA and the FPGA is connectable to the processor via a communications interface, the method comprising:

loading software that is generated according to the method according to claim 1 ; and

executing the software,

wherein the loading of the software comprises loading of the first application program into the FPGA and loading of the second application program into the processor.

9. The method according to claim 8 , further comprising partial reconfiguration of the FPGA.

10. A hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels, wherein the I/O channels are connectable to the FPGA and the FPGA is connectable to the processor via a communications interface, and wherein the hardware component is configured to perform the method according to claim 8 .

11. The method according to claim 1 , wherein the method is implemented via a computer program product having computer implemented instructions, which is loaded and executed in a data processing device.

12. A non-transitory digital storage medium having electronically readable control signals, which operates together with a programmable data processing device so that the method according to claim 1 is performed in a data processing device.

13. A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA (Field Programmable Gate Array), and a plurality of I/O (Input/Output) channels, the hardware component being connectable to a computer system, the I/O channels being connectable to the FPGA, and the FPGA being connectable to the processor via a communications interface, the method comprising:

selecting a first subset of the I/O channels for operation by the FPGA;

generating a first application program to be executed by the FPGA so as to cause the FPGA to perform an FPGA function only through the first subset of the I/O channels;

selecting a second subset of the I/O channels for operation by the processor; and

generating a second application program to be executed by the processor so as to cause the processor to perform a processor function only through the second subset of the I/O channels,

storing the second application program with the embedded first application program in a storage for execution on the processor, and

executing the first application program and the second application program,

wherein the step of generating a first application program comprises the generation of code for connecting the second subset of the I/O channels to the communications interface, thereby causing the processor to perform the processor function through the second subset of the I/O channels via the communication interface,

wherein the step of generating a second application program comprises embedding the first application program in the second application program, and

based on the executed first application program and second application program, connecting the hardware component of the computer system, wherein the hardware component includes the I/O channels, the FPGA, and the processor, with the I/O channels connecting to the FPGA, and the FPGA connecting to the processor, via the communication interface.